PLL & Clocking Glossary

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A

Altclkctrl

This megafunction is used to implement the clock power down and clock source selection features.

Altpll

This megafunction is used to implement phase-locked loops (PLLs) and the features they support.

Automatic Clock Switchover

This feature allows the PLL to automatically switch between two reference input clocks and can be used for clock redundancy or for a dual clock domain application. When the primary clock signal is not present the clock switchover circuitry automatically switches from the primary to the secondary clock for the PLL input clock reference.

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B

Bandwidth

The bandwidth of a PLL is the measure of the PLL’s ability to track the input clock and jitter. The closed-loop gain 3-dB frequency of the PLL determines the PLL bandwidth. The bandwidth is approximately the unity gain point for the PLL open loop response.

A high bandwidth PLL provides a fast lock time and tracks jitter on the reference clock source, passing it through to the PLL output. A low bandwidth PLL filters out reference clock jitter, but increases lock time.

See Programmable Bandwidth
See Reconfigurable Bandwidth

Bank Skew

Bank skew is the amount of time difference between the outputs in a particular I/O bank with a single input driving the outputs as shown in Figure 1.

Figure 1. Bank Skew

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C

Clock Feedback Mode

The clock feedback mode defines the phase alignment of the input clock versus the output clock.

See External Feedback Mode
See No Compensation Mode
See Normal Mode
See Source Synchronous Mode
See LVDS Compensation Mode
See Zero Delay Buffer Mode

Clock Power Down

This feature allows the clock signal to be enabled or disabled by using the clkena signal. The dynamic clock enable or disable feature allows the internal logic to synchronously turn on or turn off clock networks (global and regional).

Clock Source Selection

This feature allows selection of the PLL clock reference from a number of clock input sources.

Clock Switchover

The clock switchover feature allows the PLL to switch between two reference input clocks.

See Automatic Clock Switchover
See Manual Clock Switchover

Counter Cascading

Counter cascading is implemented by feeding the output of one post-scale counter into the input of the next post-scale counter in a cascade chain to create larger post-scale counter values.

Cycle-to-Cycle Jitter

For this definition and more details, go to Jitter Information.

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D

Downstream PLL

A downstream PLL is a PLL that receives a clock from another PLL-based device, including devices that use spread-spectrum.

Duty Cycle

Duty cycle is the ratio of the output high time to the total cycle time as shown in Figure 2. Duty cycle is expressed as a percentage (with 50% having equal clock high and low times). Duty cycle is important in systems that use both the rising and falling clock edges, such as with DDR.

Altera PLLs align the rising edge of the reference input clock to a feedback clock using the phase frequency detector (PFD). The falling edges are determined by the duty cycle specified by the user.

Figure 2. Duty Cycle

Duty Cycle, Programmable

Programmable duty cycle allows the designer to manipulate the position of the positive and negative edges of the clock, which simplifies set-up and hold time requirements associated with these edges.

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E

External Feedback Mode

In the external feedback mode, the external feedback input pin, fbin, is phase-aligned with the clock input pin as shown in Figure 3. Aligning these clocks allows removal of clock delay and skew between devices. In this mode, one PLL clock output feeds back to the PLL fbin input, becoming part of the feedback loop.

If the internal PLL clock outputs are used in this mode, there will be a phase delay relative to the clock input pin. When using this mode, Altera recommends using the same I/O standard on the input clock, feedback input, and output clocks.

Figure 3. Phase Relationship Between PLL Clocks in External Feedback Mode

Note:

  1. The PLL clock outputs can lead or lag the fBIN clock input.

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G

Gated Lock

See Lock, Gated.

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H

Half-Period Jitter

For this definition and more details, go to Jitter Information.

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J

Jitter

For this definition and more details, go to Jitter Information.

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L

Lock

The lock output indicates that the PLL output clock is stable and in phase with the reference clock. The two requirements for a PLL to obtain lock are that the reference clock and feedback clock are frequency matched and phase aligned.

Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock, see Figure 4.

Lock, Gated

Altera® FPGAs that support the gated lock signal include a programmable counter that holds the lock signal low for a user-selected number of input clock transitions. This allows the PLL to lock before enabling the lock signal, which eliminates the toggling of the lock signal as the PLL begins tracking the reference clock. Figure 4 shows an example of a timing waveform of the lock and gated lock signals.

Figure 4. Timing Waveform for Lock and Gated Lock Signals

LVDS Compensation Mode

The goal of this mode is to maintain the same data and clock timing relationship seen at the pins at the internal serializer/deserializer (SERDES) capture register,except that the clock is inverted (180-degree phase shift). Thus, this mode ideally compensates for the delay of the LVDS clock network plus any difference in delay between these two paths:

  • Data pin-to-SERDES capture register.
  • Clock input pin-to-SERDES capture register. In addition, the output counter needs to provide the 180-degree phase shift.

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M

Manual Clock Switchover

This feature allows the PLL to switch between two reference input clocks based on a user control signal, clkswitch. If clkswitch is low, then inclk0 is selected; if clkswitch is high, then inclk1 is selected.

Modulation Frequency

Modulation frequency is the frequency of the spreading signal, or how fast the signal sweeps from the minimum to the maximum frequency.

Modulation Profile

Modulation profile is the waveform of the spreading signal, which is the low frequency signal that is added to modulate the output. The band of frequencies over which the electromagnetic interference (EMI) energy is spread is fixed by the modulation width and does not vary with the modulation profile. Since EMI testing evaluates peaks, spreading energy evenly over the frequency band lowers EMI. A flat spectral profile with minimal peaking shows that the energy is evenly spread across the frequency band.

In Altera® FPGAs that support spread spectrum clocking, a linear, also known as triangular, modulation profile is utilized. Figure 5 shows the spectrum of the linear modulation profile.

Figure 5. Linear Modulation Profile

Modulation Width

See Spread Percentage.

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N

No Compensation Mode

In this mode, the PLL does not compensate for any clock networks. This leads to better jitter performance because the clock feedback path into the PFD does not pass through as much circuitry. Both the PLL internal and external clock outputs are phase shifted with respect to the PLL clock input. Figure 6 shows an example waveform of the PLL clocks’ phase relationship in no compensation mode.

Figure 6. Phase Relationship between PLL Clocks in No Compensation Mode

Notes:

  1. Internal clocks fed by the PLL are phase-aligned to each other.
  2. The PLL clock outputs can lead or lag the PLL input clocks.

Normal Mode

The delay introduced by the global clock network is fully compensated for in normal mode. Therefore, the PLL phase aligns the input reference clock with the clock signal at the ports of the registers in the logic array or the input/output element (IOE).

If the external clock output is used in this mode, there will be a phase delay relative to the clock input pin. Similarly, if you use the internal PLL clock outputs to drive general-purpose I/O pins, there will be a phase delay with respect to the clock input pin.

Figure 7 shows an example waveform of the PLL clocks’ phase relationship in normal mode.

Figure 7. Phase Relationship Between PLL Clocks in Normal Mode

Note:

  1. The external clock output can lead or lag the PLL internal clock signals.

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P

Period Jitter

For this definition and more details, go to Jitter Information.

Phase Shift

Setting phase shifts will shift the PLL output clock a fixed amount with respect to the absolute PLL output clock, for example a 0 degree phase shifted PLL output clock. The smallest phase shift increment is determined by the voltage controlled oscillator (VCO) period divided by eight. For VCO ranges, see the DC & Switching Characteristics chapter of the appropriate Altera device family handbook.

Phase-Locked Loop (PLL)

For this definition and more details, go to PLL Basics.

PLL Acquisition/Lock Time

The acquisition/lock time of a PLL is the amount of time required by the PLL to attain the target frequency and phase relationship after power-up, after a programmed output frequency change, or after resetting the PLL.

PLL Reconfiguration

This feature allows the user to reload the settings of the PLL, such as the counter or bandwidth values, in user mode on the fly. The user can control the PLL components to update the output clock frequency, PLL bandwidth, or phase-shift variation in real time, without the need to reconfigure the entire FPGA. PLL settings that can be reconfigured on the fly vary depending on the device family and PLL type.

Programmable Bandwidth

This feature provides advanced control of the PLL bandwidth using the programmable characteristics of the PLL loop, including the charge pump current, loop filter resistor (R) and high frequency capacitor (CH) values.

See Bandwidth.

Programmable Duty Cycle

See Duty Cycle, Programmable.

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R

Reconfigurable Bandwidth

This feature provides dynamic control of the PLL bandwidth in user-mode using the reconfigurable characteristics of the PLL loop, including the charge pump current, loop filter resistor (R) and high frequency capacitor (CH) values. These values can be reconfigured on-the-fly in user mode.

See Bandwidth.

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S

Skew

Skew is the variation in arrival time of two signals that were expected to arrive at the same time. Skew can be positive or negative, based on leading or lagging signals, as shown in Figure 8.

Figure 8. Skew Caused by Leading and Lagging Signals

In high-speed systems, clock skew greatly affects the timing margin. For example, a skew of 2 ns represents a significant portion of a 10-ns cycle time for a 100-MHz system. If the timing budget does not allow for this variation, the system data transfers may be unreliable or non-functional.

Source Synchronous Mode

In source synchronous mode, the clock to data phase relationship at the input pins is maintained at the clock and data ports of the IOE input register. This mode is recommended for source synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as the same I/O standard is used.

Figure 9 shows an example waveform of the data and PLL clocks phase relationship in source synchronous mode.

Figure 9. Phase Relationship Between Clock and Data in Source-Synchronous Mode

Spread Percentage

Spread percentage, also known as modulation width, is defined as the percentage that the PLL modulates the target frequency. With a wider modulation, the energy is distributed over a larger band of frequencies and the reduction of peak energy increases. A negative (–) percentage indicates a down spread, a positive (+) percentage indicates an up spread, and a ( ± ) indicates a center spread. Down-spread modulation shifts the target frequency down by half the spread percentage, centering the modulated waveforms on a new target frequency.

Down-spread modulation is utilized in Altera FPGAs that support spread spectrum clocking.. The maximum output frequency is specified, and the spreading results in instantaneous frequencies at or below the maximum specified. For example, a 100-MHz signal that uses 0.5 percent down-spread modulation means the output frequency will vary between 99.5 MHz to 100 MHz.

Spread-Spectrum Clocking

Spread-spectrum clocking schemes distribute the energy of the fundamental clock frequency to minimize peaking of energy at specific frequencies. This reduces the fundamental clock frequency EMI/RFI as well as the higher frequency harmonic components. Figure 10 compares the clock signal energy of a spread and non-spread signal.

Figure 10. Spread-Spectrum Signal Energy Versus Non-Spread-Spectrum Signal Energy

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Z

Zero Delay Buffer Mode

In the zero delay buffer mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. When internal PLL clock outputs (from the same PLL as the external clock output) are used in this mode, they will lead or lag the clock input and external clock output. When using this mode, Altera recommends using the same I/O standard on the input clock, and output clocks.

Figure 11 shows an example waveform of the PLL clocks’ phase relationship in zero delay buffer mode.

Figure 11. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode

Note:

  1. The internal PLL clock output can lead or lag the external PLL clock outputs.

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