Clock Networks

Each Altera® FPGA has an advanced, low-skew clock network. The number of clock networks and features offered varies depending on the device family (see Tables 1 and 2). The clock networks can be driven by CLK input pins, phase-locked loop (PLL) outputs, or internal logic, and can be used for other device-wide signals with large fan-outs, such as asynchronous clears and clock enables.

Table 1. Clock Network Features for Stratix® Devices

Feature Stratix III Stratix II Stratix II GX Stratix Stratix GX
Number of Dedicated CLK Pins1616161612
Number of Global Clock Networks1616161616
Number of Regional Clock Networks4832321616
Clock Power DownXXX--
Clock Source SelectionXXX--

Table 2. Clock Network Features for Cyclone® Devices

Feature Cyclone III Cyclone II Cyclone
Number of Dedicated CLK Pins8, 16 (1)8, 164(2)
Number of Global Clock Networks10, 20 (3)8, 168
Number of Regional Clock Networks---
Clock Power DownXX-
Clock Source SelectionXX-

Notes:

  1. EP3C5 and EP3C10 have 8 CLK pins. The larger devices have 16 CLK pins.
  2. The EP1C3 device in the 100-pin TQFP package only has 2 CLK pins.
  3. EP3C5 and EP3C10 have 10 Global Clock Networks. The larger devices have 20 Global Clock Networks.

Literature

Details about the clock networks in the Altera device families can be found in the appropriate device family handbook:

Additional related information can also be found in the following megafunction user guide: