Each Altera® FPGA has an advanced, low-skew clock network. The number of clock networks and features offered varies depending on the device family (see Tables 1 and 2). The clock networks can be driven by CLK input pins, phase-locked loop (PLL) outputs, or internal logic, and can be used for other device-wide signals with large fan-outs, such as asynchronous clears and clock enables.
- EP3C5 and EP3C10 have 8 CLK pins. The larger devices have 16 CLK pins.
- The EP1C3 device in the 100-pin TQFP package only has 2 CLK pins.
- EP3C5 and EP3C10 have 10 Global Clock Networks. The larger devices have 20 Global Clock Networks.
Details about the clock networks in the Altera device families can be found in the appropriate device family handbook:
- Clock Networks and PLLs in Stratix III Devices (PDF)
- PLLs in Stratix II and Stratix II GX Devices (PDF)
- General Purpose PLLs in Stratix and Stratix GX Devices (PDF)
- PLLs in Cyclone II Devices (PDF)
- Using PLLs in Cyclone Devices (PDF)
Additional related information can also be found in the following megafunction user guide:
- Clock Control Block (altclkctrl) Megafunction User Guide (version 2.4, Dec. 2008, 337 KB)