PLL Clock Management Features in Altera FPGAs

Altera® FPGAs offer feature-rich phase-locked loops (PLLs) that provide robust clock management capabilities and synthesis for device clock management, external system clock management, and high-speed I/O pin interfaces. The PLLs can feed the global clock network or I/O pins. One of our newest FPGA families, Stratix® V FPGAs, offer fractional PLLs (fPLLs) that deliver increased clocking flexibility and replace external voltage-controlled crystal oscillators (VCXOs).

Table 1 summarizes and compares the PLL features available in our latest FPGAs.

Table 1. PLL Features

Feature Stratix V
fPLLs
Stratix III and
Stratix IV PLLs
Stratix II and
Stratix II GX PLLs
Cyclone® IV
PLLs
Cyclone III
PLLs
Arria® II GX
PLLs
Top/
Bottom
Left/
Right
Enhanced
PLL
Fast
PLL
GPLL MPLL
Number of PLLs322-42-82-42-81-42-42-44-6
Clock Multiplication
and Division
m/(n x
post-scale counter)
m/(n x
post-scale counter)
m/(n x
post-scale counter)
m/(n x
post-scale
counter)
m/(n x
post-scale counter)
m/(n x
post-scale counter)
m/(n x
post-scale counter)
m/(n x
post-scale counter)
m/(n x
post-scale counter)
M Counter Values1-5121-5121-5121-5121-321-5121-5121-5121-512
N Counter
Values
1-5121-5121-5121-5121-41-5121-5121-5121-512
Post-Scale Counter Values1-5121-5121-5121-512 (2)1-32 (1)1-512 (2)1-512 (2)1-512 (2)1-512
Number of Internal
Clock Outputs Available
Per PLL
18107645557
Number of Dedicated External
Clock Outputs (PLL#_OUT) Available
Per PLL
4 single-ended, or
2 single-ended
and 1 differential pair
6 single-ended, or
4 single-ended
and 1 differential pair
2 single-ended, or
1 differential pair
6 single-
ended, or 3 differential pairs
(3)1 single-ended, or 1
differential pair
1 single-ended, or 1
differential pair
1 single-ended, or
differential
1 single-ended, or 1 differential pair; 3 single-ended or 3 differential pairs (4)
Number of Feedback Clock Inputs Available Per PLL1 single-ended or differential1 single-ended or differential1 single-ended only1 single-ended or
differential
-----
PLL Outputs Can Drive All Clock Network Types---XXXXX-
Supported Clock Feedback Modes
Normal ModeXXXXXXX (5)XX
No Compensation ModeXXXXXXXXX
Zero Delay Buffer ModeXXXX-XX (5)XX
External Feedback ModeXXXX-----
Source-Synchronous ModeXXXXXXX (5)XX
LVDS Compensation ModeX-X-----X
Deterministic Latency CompensationX----X (6)X--
Features
Phase ShiftDown to 67-ps incrementsDown to 96.125-ps incrementsDown to 96.125-ps incrementsDown to 125-ps incrementsDown to 125-ps incrementsDown to 96-ps incrementsDown to 78-ps increments (7)Down to 96-ps incrementsDown to 96.125-ps increments
Per Tap Programmable Phase Shift Allowed in All ModesXXXXXXXXX
Advanced Control Signals (pllena, areset, pfdena)XX (8)X (8)XXX (8)X (8)X (8)X (8)
Programmable Duty CycleXXXXXXXXX
Advanced Features
Gated Lock---XX----
Automatic Clock SwitchoverXXXX-XXXX
Manual Clock SwitchoverXXXXXXXXX
Programmable BandwidthXXXXXXXXX
PLL ReconfigurationXXXXXXXXX
Spread Spectrum ClockingXXXX-XXXX
Counter CascadingXXXX-XXXX
Ability to Internally Cascade PLLsXXXXXXXXX
Supported PLL Drivers
Dedicated Input Clock PinXXXXXXXXX
GCLK Network(9)XXXXXXXXX
RCLK Network(9)XXXXX---X

Notes:

  1. C counters range from 1 through 32 if the output clock uses a 50 percent duty cycle. For any output clocks using a non-50 percent duty cycle, the post-scale counter ranges from 1 through 16.
  2. C counters range from 1 through 512 if the output clock uses a 50 percent duty cycle. For any output clocks using a non-50 percent duty cycle, the post-scale counter ranges from 1 through 256.
  3. The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock (txclkout).
  4. PLL5 and PLL6 do not have dedicated clock outputs. The same PLL clock output drives three single-ended or three differential I/O pairs. This is only supported in PLL_1 and PLL_3 of the EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
  5. This is not applicable for MPLL5 and MPLL6.
  6. This is not applicable for GPLL3 and GPLL4.
  7. This is only applicable when MPLLs are used for transceiver clocking.
  8. pllena feature is not supported in Stratix IV, Stratix III, Arria II GX, Cyclone IV, and Cyclone III devices.
  9. The global (GCLK) or regional (RCLK) clock input can be driven by an output from another PLL, a clock pin-driven global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal or general purpose I/O pin cannot drive the PLL.

To view the PLL features available in all Altera FPGAs, refer to PLL Features in Altera FPGAs.

Documentation

Detailed information about the PLLs available in the Altera device families can be found in the appropriate device family handbook:

Additional related information is available in the following documents and web page: