As FPGAs increase in performance, size, and complexity, the verification process can become a critical part of the FPGA design cycle. To alleviate the complexity of the verification process, Altera provides a portfolio of on-chip debugging tools. The on-chip debugging tools allow real-time capture of internal nodes in your design to help you verify your design quickly without the use of external equipment.
For resources on on-chip debugging, see the following:
For a brief overview of the on-chip debugging portfolio of tools and the chip planner, refer to the SignalTapTM II Embedded Logic Analyzer section on the Verification and Board Level product pages.
To search for known on-chip debugging issues and technical support solutions, use Altera's Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
On-chip Debugging Resources
Table 1 provides links to available documentation about on-chip debugging tools.