Intel® FPGA IP for Configuration - Support Center

Welcome to the Intel® FPGA Intellectual Property (IP) for Configuration Support Center!

Here you will find information on how to select, design, and implement configuration schemes and features. There are also guidelines on how to bring up your system and debug the configuration links. This page is organized into categories that align with a configuration system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Stratix® 10Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation ArchiveTraining CoursesVideos and WebcastsDesign Examples, and Knowledge Base.

Table 1 - Configuration Schemes and Features Overview

Device Family

Configuration Schemes

Configuration Features

Scheme

Data Width (bits)

Max Clock Rate (MHz)(1)

Max Data Rate (Mbps)(1)

Design Security

Partial Reconfiguration (4)

RSU

SEU

CvP

Intel®  Stratix®  10

Avalon®-ST

32

125

4,000

 

16

125

2,000

 

8

125

1,000

 

Active Serial (AS)(2)

4

133(3)

532

 √

SD/MMC

8

50

400

 

NAND

8

50

400

 

JTAG

1

30

30

 

Intel®  Arria®  10

JTAG

1

33

33

 

(5)

 

Active Serial (AS)(2)

1

100

400

(5)

4

Passive Serial (PS)

1

100

100

(5)

PFL IP core

 

Fast Passive Parallel (FPP)

8

100

3,200

 

 

(6)

 

PFL IP core

 

 

16

32

Configuration via HPS

16

100

3,200

(6)

 

 

32

Intel®  Cyclone®  10 GX

JTAG

1

33

33

 

(5)

 

Active Serial (AS)(2)

1

100

400

(5)

4

Passive Serial (PS)

1

100

100

(5)

PFL IP core

 

Fast Passive Parallel (FPP)

8

100

3,200

 

 

(6)

PFL IP core

 

16

32

Intel®  Cyclone®  10 LP

JTAG

1

25

25

 

 

 

 

Active Serial (AS)

1

40

40

 

 

 

Passive Serial (PS)

1

66(7)/133(8)

66(7)/133(8)

 

 

 

 

Fast Passive Parallel (FPP)

8

66(7)/100(9)

528(7)/800(9)

 

 

 

 

Notes:
 
  • RSU - remote system update
  • SEU - single event upset
  • CvP - configuration via protocol
  • PFL - parallel flash loader
  1. The maximum clock rate and maximum data rate are preliminary.
  2. Supported configuration from EPCQ-L devices only.
  3. The maximum clock rate when using an external configuration clock source is 133 MHz. The maximum clock rate reduces if you use the internal oscillator as the configuration clock source, during SmartVID operation, or when the device is in user mode.
  4. You can perform partial reconfiguration after the device is fully configured. For more information, refer to the Creating a Partial Reconfiguration Design chapter in volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.
  5. Partial configuration can be performed only when it is configured as internal host.
  6. Supported at a maximum clock rate of 100 MHz.
  7. Supply voltage for internal logic, VCCINT = 1.0V
  8. Supply voltage for internal logic, VCCINT = 1.2V
  9. Supply voltage for internal logic, VCCINT = 1.2 V. Cyclone 10 LP 1.2 V core voltage devices support 133 MHz DCLK fMAX for 10CL006, 10CL010, 10CL016, 10CL025, and 10CL040 only.

Intel® Stratix® 10 Devices

Intel® Stratix® 10 Devices

Intel® Stratix® 10 Devices

Intel Stratix® 10 Devices

  • Intel Stratix 10 Remote Update IP Core User Guide - coming soon
Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

Intel Stratix® 10 Devices

  • Intel Stratix 10 Device Security User Guide - To obtain the user guide, contact your Intel sales representative.
Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

Intel Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

Intel Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

Intel Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

Intel Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 GX Devices

Intel® Cyclone® 10 LP Devices

  • Training Courses  (Search using the keywords configuration, partial reconfiguration, and single-event upsets)
Title  Description
Configuration via Protocol (CvP) Watch this video to learn how to configure your Intel® Arria® 10 device using the PCIe* protocol.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1 Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2 Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Perform Active Serial (AS) Configuration via JTAG Interface Using Serial Flash Loader IP Core   Watch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core.
A tool for configuration failures, design security, and error detection cyclic redundancy check (CRC). The tool supports Intel® Arria® 10 FPGAs and SoCs, but not Intel Stratix® 10 devices.
  • Configuration Diagnostic Tool ( To get this tool, please contact your Intel sales representative)
FPGA configuration failure? Use this troubleshooter to identify possible causes.

Note: The default device is Intel® Stratix® 10 devices. For Intel Arria® 10 devices, please change the device selection in the Quick Filter.

Note:

1. To obtain the support readiness for configuration schemes, features and IPs, contact your Intel sales representative. 

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