External Memory Interfaces Support Center

Welcome to the External Memory Interface (EMIF) support page! Here you will find information on how to plan, design, and implement your external memory interfaces, as well as a few tips and tricks for debugging purposes.

This page is set up to walk you through from start to finish when designing and implementing an external memory interface. In the Device Selection and IP Generation section you will find resources to help you select a device that will meet your memory interface requirements as well as details regarding EMIF IP and example design generation. The Board Design and System-Level Timing Closure section will provide information on how to layout and design your board, as well as guidance on how to simulate and determine your board timing parameters to achieve system-level timing closure. The Debug section will provide you with some tools and resources for debugging any issues you may encounter, and the Recommended Reading and Training section contains documents and training courses that the user might find helpful during this entire process.

 

Getting Started
Overview

This section is intended to assist users in planning their External Memory Interface (EMIF) design. Here you will find information to help you select a device/package that can support your memory requirements, guidelines to help with the intellectual property (IP) generation process, documentation to help with pin planning, and much more! The recommended flow for this stage in the EMIF design process is as follows:

EMIF Device Selector

The EMIF Device Selector helps to determine which Intel® Arria® 10 or Intel® Stratix® 10 device will meet your memory interface needs. This tool takes a few parameters as input, such as the desired memory protocol and interface width, and provides a list of all the Arria 10 or Stratix 10 devices that will meet your EMIF requirements while also providing the I/O and transceiver count for each device/package. This tool also contains a bandwidth feature that will calculate the number of external memory interfaces needed to achieve a desired bandwidth and efficiency.

EMIF Spec Estimator

The EMIF Spec Estimator assists you in determining which Intel FPGA will meet your EMIF performance requirements. This tool compares performances across all FPGAs side-by-side based on your search criteria, such as desired memory protocol and frequency. While the Device Selector tool assists users in determining which device and package will meet their external memory interface requirements, the EMIF Spec Estimator allows users to determine which FPGA device speed grade will meet their specific performance criteria. In addition, there is also a short 3-minute video covering how to use the Spec Estimator and its benefits located below.

EMIF Example Design Guidelines

The EMIF Example Design Guidelines provides step-by-step instructions on how to generate the EMIF IP and how to create a reference example design. Included below is a 4-minute video that walks you through the parameterization of the EMIF IP as well as the EMIF example design generation process. Please note that if your EMIF solution contains multiple external memory interfaces, you should also refer to the Multiple EMIF Example Design guide below.

Multiple EMIF Design Guide

The Multiple EMIF Example Design Guide is a step-by-step guide showing users how to integrate multiple Arria 10 EMIF IPs into a single Qsys design. Although this guide is focused on the Arria 10 EMIF IP, it is applicable to Stratix 10 as well. There is also a 4-minute video that walks you through the steps mentioned in the guide.

EMIF Simulation Guidelines

The EMIF Simulation Guidelines contains instructions on how to generate an EMIF simulation example design and how to run simulations using the ModelSim*-Intel FPGA simulation software.

EMIF Pin Guidelines

The EMIF Pin Guidelines serves as a quick reference guide for all memory interface pin placement restrictions (focusing mainly on DDR3 and DDR4 interfaces). This document includes information on arranging address/command/control and data pins, I/O bank placement restrictions, and much more! The Pin Guidelines helps you to prepare for board design by providing you with necessary information regarding the layout and placement of your external memory interfaces. If you are using the Intel Quartus® Prime Pro software, please also refer to the BluePrint Platform Designer video links under the Fitter Check section below for easy memory interface placement.

Note

If you do not have access to Quartus Prime Pro and the BluePrint Platform Designer, you can verify the placement of your external memory interfaces by running the Fitter in the Quartus Prime software. If your design successfully passes the Fitter stage, then your selected device and package can fit your external memory interfaces.

BluePrint Platform Designer

The BluePrint Platform Designer is an easy-to-use tool in Quartus Prime Pro that simplifies the placement of external memory interfaces using a drag-and-drop feature and is supported for the Arria 10 and Stratix 10 device families. These short 3-minute videos cover the benefits of using BluePrint for I/O placement and provides instructions on how to use BluePrint for external memory interfaces.

HPS EMIF Guidelines

The Hard Processor Subsystem (HPS) EMIF Guidelines provides information regarding HPS EMIF limitations, IP generation, and pin constraints.

DDR4 Ping Pong PHY

Ping Pong PHY is a relatively new feature that allows two memory interfaces to share address and command buses. This is supported for DDR3 and DDR4 protocols and for the Stratix V, Arria 10, and Stratix 10 device families. This short 5-minute video covers the concept of Ping Pong PHY, what its benefits are, and also reviews simulation results!

PHYLite Group Pin Placement

PHYLite allows users to build custom memory interface PHY blocks in Arria 10 or Stratix 10 devices. This solution allows you to interface with external memory devices that may not be supported with EMIF IP, such as TCAM, Flash, Mobile DDR, and more! This short 3-minute video covers how to properly assign the pinouts for PHYLite based on different DQ/DQS group sizes. Although this video focuses mainly on the Arria 10 product family, it is applicable to Stratix 10 devices as well.

PHYLite OCT Block for Calibrated Termination I/O Buffer

The PHYLite IP supports many different I/O standards and termination values on input and output buffers for Arria 10 and Stratix 10 product families. When calibrated termination values are selected on the I/O buffer, you are required to connect the RZQ pin from the On-Chip-Termination (OCT) block to an external resistor. However, during PHYLite IP generation, the OCT block is not automatically created. This short 4-minute video covers how to create an OCT block and associate it with the terminated I/O buffer in the PHYLite IP. 

Getting Started
Overview

This section is intended to help users design their boards optimally for external memory interfaces. Here you will find information on board design, channel simulation, board skew, and much more! The recommended flow for board design and achieving system-level timing closure is as follows:

EMIF Board Guidelines

The EMIF Board Guidelines serves as a quick reference guide for all external memory interface routing and layout recommendations. This document contains information on trace impedance, routing suggestions to minimize PCB layer propagation variance, and layout and spacing recommendations to reduce skew for address/command, clock, and data signals.

EMIF Pin Guidelines

The EMIF Pin Guidelines serves as a quick reference guide for all memory interface pin placement restrictions (focusing mainly on DDR3 and DDR4 interfaces). This document includes information on arranging address/command/control and data pins, I/O bank placement restrictions, and much more! The Pin Guidelines helps you to prepare for board design by providing you with necessary information regarding the layout and placement of your external memory interfaces.

Channel Simulation Guidelines

The Channel Simulation Guidelines assists users in performing channel and board simulations with regards to external memory interfaces. This document covers topics such as measuring write and read intersymbol interference and crosstalk, arranging address/command/control and data pins, I/O bank placement restrictions, and much more!

Channel Loss Tool

The Channel Loss Tool calculates the channel loss due to intersymbol interference and crosstalk on address/command, read, and write signals. This tool is only compatible with the HyperLynx Signal Integrity software and DDRx Batch Simulation results. The Channel Loss Tool takes the results produced from board simulation and calculates the intersymbol interference and crosstalk values that are needed during EMIF IP generation.

Board Skew Parameter Tool

The Board Skew Parameter Tool calculates the board skew due to PCB traces and/or multi-rank designs. This tool takes information regarding your board's trace delays as input and calculates the address/command, clock, and data skew values that are needed during EMIF IP generation. Included below is a short 4 minute video that showcases how to use the Board Skew Parameter Tool.

Note

In order to verify your design will achieve system-level timing closure, you should compile your EMIF design and make sure that the generated report does not contain any failures. Specifically, you need to verify that there are no failures in the Report DDR Timing analysis.

EMIF Timing Closure Guidelines

The EMIF Timing Closure Guidelines contains details on EMIF timing paths and the DDR Timing Report used to verify system-level timing closure.

Getting Started
Overview

This section is intended to help users debug any issues regarding their external memory interfaces. Here you will find documentation on available debug tools to help diagnose any issues you may encounter. To determine if you should use the EMIF Debug Toolkit or the EMIF Debug GUI for debugging purposes, please refer to the following:

  EMIF Debug Toolkit EMIF Debug GUI
Features - Displays pre and post calibration margins per DQS group and DQ pin
- Generates read/write eye diagrams per DQ pin
- Allows customizable real-time traffic generator for test/debug (Traffic Generator 2.0)
- Captures read/write margins during user-mode traffic (Driver Margining)
- Displays post-calibration margins per DQ pin
- Sweeps ODT to find optimal termination setting (ODT Tuning)
- Calculates effective EMIF example design bandwidth (Efficiency Calculator)
Support - Compatible with EMIF example design project and custom EMIF designs containing one or more memory interfaces
- Supports all memory protocols
- Compatible only with the EMIF example design project
- Supports DDR3, DDR4, and QDRIV memory protocols only
Accessibility - Accessible through Quartus Prime software (Tools > System Debugging Tools > External Memory Interface Toolkit) - Accessible through Quartus Prime software (Tools > System Debugging Tools > System Console)
- Refer to EMIF Debug GUI section below
Debugging Multiple EMIFs Guide

One of the debugging resources available in the Quartus Prime software is the EMIF Debug Toolkit, which helps to diagnose problems by providing monitoring reports and margining data regarding your external memory interfaces. The Debugging Multiple EMIFs Guide provides step-by-step instructions on how to daisy-chain multiple memory interfaces for compatibility with the EMIF Debug Toolkit.

2-D Eye Diagram

The Read/Write 2-D Eye Diagram is a feature available in the Quartus Prime EMIF Debug Toolkit. It allows users to generate read and write eye diagrams for each data pin. This short 3 minute video covers important voltage reference parameters during the EMIF IP generation process and how to use the EMIF Debug Toolkit to generate read and write eye diagrams for every data pin.

Traffic Generator 2.0

The Traffic Generator 2.0 is a new feature available within the Quartus Prime EMIF Debug Toolkit. It allows users to emulate traffic to external memory and contains the ability to run customizable traffic and test patterns for test and debug. The guide provides step-by-step instructions on how to setup your EMIF IP to allow for Traffic Generation 2.0 support as well as directions on how to setup and use the different capabilities the tool has to offer. Included below is also a series of 3 minute videos that cover how to enable and configure Traffic Generator 2.0, as well as some use-cases where this feature can prove to be useful during debug.

Driver Margining

Driver Margining is a feature available in the Quartus Prime EMIF Debug Toolkit. It allows users to capture read and write margining data per pin during user-mode traffic. These short 3 minute videos cover the differences between driver margining and calibration margining, as well as instructions on how to use the driver margining feature in the EMIF Debug Toolkit.

Arria 10 EMIF Debug GUI Guide

The Arria 10 EMIF Debug GUI is a system console based tool that is compatible with DDR3, DDR4, or QDRIV EMIF example designs. The GUI contains an ODT tuning feature that helps the user to find the optimal termination setting for their memory interface. This is done by iterating through all possible termination combinations (output drive strength, Dynamic ODT, Rtt Nominal, and Rtt Park settings) in order to find the most ideal setting. The Arria 10 EMIF Debug GUI also contains an efficiency calculator that measures the efficiency and effective bandwidth of your external memory interface. This guide provides step-by-step instructions on how to use the Arria 10 EMIF Debug GUI, as well as the necessary files needed to access the tool.