Intel® FPGA IP for PCI Express* – Support Center

Welcome to the Intel® FPGA intellectual property (IP) for PCI Express* (PCIe*) support center!

Here you will find information on how to select, design, and implement PCIe links. There are also guidelines on how to bring up your system and debug the PCIe links. This page is organized into categories that align with a PCIe system design flow from start to finish.  

Enjoy your journey!

Refer to Table 1 and Table 2 to understand the PCIe* support for Intel® Stratix® 10 and Intel® Arria® 10 devices. Compare between the two devices to select the right device for your PCIe system implementation.

Table 1 - Device Support and Number of Hardened PCIe IP Blocks
Device Family Number of Hardened PCIe IP Blocks PCIe Speed per Lane

Gen1

(2.5 GTps)

Gen2

(5.0 GTps)

Gen3

(8.0 GTps)

Intel® Stratix® 10 1 to 4 per device check mark check mark check mark
Intel® Arria® 10 1 to 4 per device check mark check mark check mark
Table 2 - Device Configuration and Feature Support
Interface Type Avalon® Streaming (Avalon®-ST) Interface Avalon® Memory-Mapped (Avalon®-MM) Interface CvP / PRoP
Device Family IP Configuration Avalon®-ST Avalon® -ST SR-IOV Avalon®- MM Avalon®-MM DMA

 

Intel® Stratix® 10 Endpoint Up to Gen3x16 Up to Gen3x16 Up to Gen3x16 Up to Gen3x16 Up to Gen3x16
CvP Initialization, Update, and PRoP
Root Port Up to Gen3x16 NA Up to Gen3x16 NA NA
Intel® Arria® 10 Endpoint Up to Gen3x8 Available Up to Gen3x4 Gen1x8, Gen2x4, Gen2x8, Gen3x2, Gen3x4, Gen3x8 Up to Gen3x8
CvP Initialization and PRoP only
Root Port Up to Gen3x8 NA Up to Gen3x4 NA NA
Notes:
  • CvP –  Configuration via Protocol
  • PRoP – Partial Reconfiguration over PCI Express
  • SR-IOV – Single Root I/O Virtualization
  • DMA – Direct Memory Access

Intel® Arria® 10 Device and Intel Stratix 10 Device Hardened IP for PCIe

The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack, which includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional soft logic blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.


Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

Refer to the Getting Started section and Physical Layout of Hard IP section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

Title Description
Intel® Arria® 10 Device Configuration via Protocol (CvP) Learn how to configure your Intel® Arria® 10 device using the PCIe protocol.
PCIe Avalon®-MM Master DMA Reference Design in Intel® Arria® 10 Device (Part 1)  Learn how to set up the PCIe Avalon® Memory Mapped (Avalon®-MM) DMA reference design hardware in Intel® Arria® 10 devices for both the Linux* and Windows* operating systems from this Part 1 video.
PCIe Avalon®-MM Master DMA Reference Design in Intel® Arria® 10 Device (Part 2) Learn how to set up the PCIe Avalon®-MM Master DMA reference design hardware in Intel® Arria® 10 devices for both the Linux* and Windows* operating systems from this Part 2 video.

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