Intel® Quartus® Prime Design Software - Support Center

Welcome to the Intel® Quartus® Prime Design Software Support Center.

The Intel® Quartus® Prime Design Software Suite encompasses all software design tools needed to bring your Intel® FPGA from concept to production. The topics on this web page will guide you through all of the Intel® Quartus® Prime software features. Select your area of interest and navigate to the specific resources you need in the Intel® Quartus® Prime design flow.

The Intel® Quartus® Prime software comprises all the software tools you need to define, simulate, implement, and debug your FPGA design. To get started, click on the buttons below to download and license the software, and to get some quick-start guidance. Then, review some of the training materials offered for the Intel® Quartus® Prime software – from short online tutorials to full day-long instructor-led classes.

What's the difference between Standard and Pro Edition?

In the "Getting Started" section, we list the basic resources to get you started, including quick start guides, a link to basic documentation, and a link to the online and instructor-led training courses that are available.

Intel offers several types of training, both online and in-person to help get you up to speed quickly on the Intel® Quartus® Prime design flow. Here are some suggested training classes to get you started.

Intel® Quartus® Prime Software Training

Course Name

Type Duration Course Number
Using the Quartus® Prime Software: An Introduction Online 81 Minutes ODSW1100
The Quartus® Prime Software: Foundation (Standard Edition)
Online 8 Hours ODSW1110
The Quartus® Prime Software: Foundation (Pro Edition)
Online 8 Hours ODSW1110PRO
Intel® Quartus® Prime Software: Pro Edition Features for High-End Designs Instructor-Led / Virtual Class 8 Hours IPRO
The Intel® Quartus® Prime Software: Foundation Instructor-Led / Virtual Class 8 Hours IDSW110

Many more training courses are available. For a full catalog, see the Intel® FPGA Training page.

I/O planning is done at an early stage in FPGA design to ensure a successful placement in your target device while meeting dedicated pin and timing constraints. The Intel® Quartus® Prime Pro Edition software offers two tools to manage the complex process of meeting the many constraints of I/O placement. 

Tool  I/O Planning Task  How to Access 
Interface Planner Plan interfaces and device periphery  Tools > Interface Planner 
Pin Planner Edit, validate, or export pin assignments  Assignments > Pin Planner 

Interface Planner manages the complexity of integrating multiple modules with hard requirements for pin assignments (for example, PCI Express*, DDR, and phase-locked loop (PLL) intellectual property (IP) cores). The Interface Planner interacts dynamically with the Intel® Quartus® Prime Fitter to verify placement legality while you plan. You can evaluate different floorplans using interactive reports to accurately plan the best implementation.

Pin Planner is a low-level pin assignment tool. Use this to manually place I/O pins and to specify slew rate and drive strength.

I/O Planning - Training Classes

Course Type Duration Course Number
Fast & Easy I/O System Design with BluePrint Free, Online 40 minutes OBLUEINTRO

I/O Planning - Other Resources

I/O planning involves many considerations especially when high-speed I/Os or specific protocols are involved. For more information on I/O management and board development support, visit the I/O Management, Board Development Support, and Signal Integrity Analysis Resource Center web page.

You can express your design using several design entry methods:

  • Using a hardware description language (HDL)
    • Verilog 
    • SystemVerilog 
    • VHDL 
  • Platform Designer, a graphical entry tool for connecting complex modules in a structured way
  • Other high-level entry methods 

Intellectual Property

In addition to direct design entry, Intel® FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in Intel® FPGAs. 

Intel offers several HDL training courses, from free online overviews to full day-long instructor-led classes.

Course Type Duration Course Number
Introduction to Verilog HDL
8 Hours
Instructor-Led
IHDL120
Introduction to VHDL
8 Hours
Instructor-Led
IHDL110
Verilog HDL Basics
50 Minutes
Online, Free OHDL1120
VHDL Basics
92 Minutes
Online, Free OHDL1110
Advanced Verilog HDL Design Techniques
8 Hours
Instructor-Led 
IHDL230
Advanced VHDL Design Techniques
8 Hours
Instructor-Led 
IHDL240
SystemVerilog with the Quartus® II Software
38 Minutes
Online, Free
OHDL1125

The Intel® Quartus® Prime software offers several templates for commonly used logic elements such as registers, selected signal assignments, concurrent signal assignments, and subprogram calls. Templates are available in Verilog, SystemVerilog, and VHDL.

If you are unsure of the best way to write a specific function to ensure that it will be implemented correctly, you should refer to these templates. The template system is fully described in the Inserting HDL Code from a Provided Template section in volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.

Intel® FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in Intel® FPGAs. Each IP includes a simulation model for design verification before device implementation. See the following links for more information on available IP cores and the IP ecosystem within the Intel® Quartus® Prime software.

Intellectual Property Resources

Resource Description
Intel® FPGA IP Portfolio Overview of Intel® FPGA IP portfolio
Introduction to Intel® FPGA IP Cores How the IP catalog and parameter editor manage IP cores in the Intel® Quartus® Prime software
Intel® FPGA IP Finder A comprehensive list of Intel® FPGA IP cores

When a register's data setup or hold time is violated, that register may enter a state in which the register output value is unknown. The register is said to be in a metastable state. This may happen when a signal is transferred between circuitry in unrelated or asynchronous clock domains.

To ensure a reliable operation, the input to a clocking regime must be synchronized for use. Metastability will decay into a known state after some period. The usual method for treating a metastable signal is to synchronize it through several pipeline stages. Because the time for a metastable state to become stable is probablistic, the Intel® Quartus® Prime software calculates the mean time between failures (MTBF) based on the timing constraints found in the signal-to-clock relationships of registers and on the intrinsic metastability characteristics of the particular device used.

For more information on metastability analysis in the Intel® Quartus® Prime software, see the Managing Metastability with the Intel® Quartus® Prime Software chapter in volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.

For more information on metastability in FPGAs and how to mitigate the effects of metastability, see the Understanding Metastability in FPGAs white paper.

The Platform Designer is a graphical, system integration tool that allows you quickly integrate a system of complex components.

Using a standardized interconnection framework (Avalon® or AMBA* AXI*), you can integrate intellectual property from third parties, from your own organization's IP, or from black-box modules yet to be defined. All Intel® FPGA IP cores are compliant with Platform Designer interface specifications.

The Platform Designer generates the HDL for instantiation into the rest of your FPGA design.

Platform Designer Documentation

Resource Description
Creating a System with Platform Designer
Basics of using the Platform Designer
Creating Platform Designer Components
How to integrate intellectual property (IP) components for use in the Platform Designer
Platform Designer Interconnect
Details on the memory-mapped and streaming interfaces available in the Avalon® and AMBA* AXI* interconnection standards
Optimizing Platform Designer System Performance
Optimizing pipelines and dealing with bus arbitration in a Platform Designer system
Component Interface Tcl Reference Application programming interface (API) reference for integrating IP into the Platform Designer system
Platform Designer System Design Components
Description of the interconnection components availabe in the Platform Designer

Platform Designer (formerly Qsys) Training Courses

Course Duration Type Course Number
Creating a System Design with Qsys
37 Minutes
Free, Online
OQSYSCREATE
Introduction to Qsys
26 Minutes
Free, Online OQSYS1000
Introduction to the Platform Designer System Integration Tool
8 Hours
Instructor-Led
IQSYS101
System Design with Qsys Pro
42 Minute
Free, Online
OQSYSPRO
Advanced System Design Using Qsys: Component & System Simulation
28 Minutes
Free, Online
OAQSYSSIM
Advanced System Design Using Qsys: Qsys System Optimization
32 Minutes
Free, Online
OAQSYSOPT
Advanced System Design Using Qsys: System Verification with System Console
25 Minutes
Free, Online
OAQSYSSYSCON
Advanced System Design Using Qsys: Utilizing Hierarchy in Qsys Designs
22 Minutes
Free, Online
OAQSYSHIER
Advanced Qsys System Integration Tool Methodologies
8 Hours
Instructor-Led
IQSYS102
Custom IP Development Using Avalon® and AXI* Interfaces
113 Minutes
Free, Online
OQSYS3000

Platform Designer Design Examples

Resources Description
Platform Designer - Design Example Downloadable design example of a memory tester implemented in the Platform Designer.
AXI* Memory Design Example AMBA* AXI*-3 Slave interface on a simple Verilog custom memory component.
BFM Simulation Example: HPS AXI* Bridge Interface to FPGA Core A hard processor system (HPS) interface to the FPGA AXI* bridge (h2f).

Avalon® Verification IP Suite User Guide (PDF)
Design files (.zip)

Bus functional models (BFMs) to verify IP cores using Avalon® interfaces.

Mentor Graphics* AXI* Verification IP Suite (PDF)

BFMs to verify IP cores using AMBA* AXI* interfaces.

White Papers

Resource Description
Comparing IP Integration Approaches for FPGA Implementation Discusses the interconnection challenges in complex FPGA devices.
Applying the Benefits of Network on a Chip Architecture to FPGA System Design  Describes the advantages of network on a chip (NoC) architectures in Intel® FPGA system design.

The Intel® Quartus® Prime software supports RTL and gate-level design simulation in supported EDA simulators.

Simulation involves:

  • Setting up your simulator working environment
  • Compiling simulation model libraries
  • Running your simulation

The Intel® Quartus® Prime software supports the use of a scripted simulation flow to automate simulation processing in your preferred simulation environment. 

In the Intel® Quartus® Prime Standard Edition software, you have the option of using the NativeLink tool flow, which automates the launch of your chosen simulator.

The integration of a HDL simulator into the Intel® Quartus® software tool flow is described in the following section of the Intel® Quartus® software handbook:

When using the Platform Designer to configure IP cores and systems, simulation environment setup scripts are generated for supported EDA simulators.

When creating multiple Platform Designer systems, you should run "Generate Simulator Setup Script for IP" to create a combined script for your systems in the Platform Designer. 

You can incorporate generated IP core simulation scripts into a top-level simulation script that controls the simulation of your entire design. After running ip-setup-simulation, use the following information to copy the template sections and modify them for use in a new top-level script file.

You can also refer to the following videos for guidance on setting up simulations.

Simulation Resources

Resource Type Description
Simulating Intel® FPGA Designs (Intel® Quartus® Prime Pro Edition) Intel® Quartus® Prime Pro Edition Handbook Main documentation for the Intel® Quartus® Prime Pro Edition software
Simulating Intel® FPGA Designs (Intel® Quartus® Prime Standard Edition)
Intel® Quartus® Prime Standard Edition Handbook
Main documentation for the Intel® Quartus® Prime Standard Edition software
Generating a Testbench with the Altera-ModelSim* Simulation Tool
Demonstration Video  
Simulating a Nios® II Processor Design
Demonstration Video
 
How to Simulate Active Serial Memory Interface Block
Demonstration Video
 
Generating PHYLite Example Design Simulation in ModelSim* in 16.1 with Arria® 10
Demonstration Video
 
How to Simulate Cyclone® V 8b10b IP Byte Ordering
Demonstration Video
 
Simulating Arria® 10 RLDRAM3 Using the Vendor Memory Model
Demonstration Video
 
Ping Pong PHY DDR3 Simulation
Demonstration Video
 
Simulation of SoC HPS DDR3 Core
Demonstration Video
 
Advanced System Design Using Qsys: Component & System Simulation
Online, Free Training 28-minute online course (OAQSYSSIM)
Simulating Designs with 3rd Party EDA Simulators (Legacy Course)
Online, Free Training
35-minute online course (ODSW1122)

The Intel® Quartus® Prime Standard Edition software supports these EDA Simulators:

  • Aldec Active-HDL
  • Aldec Riviera-PRO
  • Cadence Incisive Enterprise
  • Mentor Graphics* ModelSim*-Intel FPGA (bundled with the Intel® Quartus® Prime software)
  • Mentor Graphics* ModelSim* - PE
  • Mentor Graphics* ModelSim* - SE
  • Mentor Graphics* QuestaSim
  • Synopsys* VCS and VCS MX

The integration of a HDL simulator into the Intel® Quartus® software tool flow is described in the Simulating Intel FPGA Designs section in volume 3 of the Intel® Quartus® Prime Pro Handbook.

The Logic Synthesis stage of the Intel® Quartus® software design flow will take the register transfer level (RTL) code and create a netlist of lower level primitives (the post-synthesis netlist). The post-synthesis netlist will then be used as an input to the Fitter, which will place and route the design.

The Intel® Quartus® Prime and Quartus® II software include advanced integrated synthesis and interfaces with other third-party synthesis tools. The software also offers schematic netlist viewers that you can use to analyze a structure of a design and see how the software interpreted your design. 

Synthesis results can be viewed with the Quartus® Netlist viewers, both after RTL elaboration and after Technology Mapping.

Synthesis Documentation

Title Description
Quartus Prime Integrated Synthesis The Intel® Quartus® Prime software integrated synthesis tool supports the synthesis of VHDL, Verilog, SystemVerilog, and legacy Altera-specific design entry languages. 
Synplify Support The Intel® Quartus® Prime software tool flow also supports the Synplicity Synplify and Synplify Pro logic synthesizers. 
Mentor Graphics* Precision RTL Support The Intel® Quartus® Prime software tool flow also supports the Mentor Graphics* Precision RTL Synthesizer. 

Synthesis Training and Demonstrations

Title Description
Using the Quartus® Prime Software: An Introduction
(ODSW1100)

Become familiar with the basic Quartus® Prime software design environment. You will learn about a basic FPGA design flow and how to use the Quartus® Prime software in the flow. 

This is a 1.5-hour online course.

The Quartus® Prime Software Design Series: Foundation
(Standard) (ODSW1110)

Learn to use the Quartus® Prime software to develop an FPGA or CPLD design from initial design to device programming. 

This is a 3.5-hour online course.

The Quartus® Prime Software Design Series: Foundation
(IDSW110)

 

Create a new project, enter design files, compile, and configure your device to see the design working in-system. Enter timing constraints and analyze a design using the Timing Analyzer. Discover how the software interfaces with common EDA tools used for synthesis and simulation.

This is an 8-hour instructor-led course.

Intel's high-level synthesis (HLS) tool takes in a design description written in C++ and generates RTL code that is optimized for Intel® FPGAs.

For more information on the Intel® HLS Compiler, including documentation, examples, and training courses, view the HLS Support Page.

HLS Documentation

Document Description
HLS Getting Started Guide
Shows how to initialize your high-level synthesis compiler environment. Also includes design examples and tutorials to demonstrate ways to effectively use the compiler.
HLS User Guide
Provides instructions on synthesizing, verifying, and simulating IP cores for Intel® FPGA products.
HLS Reference Manual
Provides information about the high-level synthesis (HLS) component design flow, including command options and other programming elements you can use in your component code.
HLS Best Practices Guide
Offers tips and guidance on how to optimize your component design using information provided by the HLS compiler.

With the Intel® Quartus® Prime Pro Edition software, the Fitter does its work in individually controllable stages; you can optimize each stage individually by running just that stage of the fitter process, iterating to optimize that stage.

Fitter Stages

Fitter Stage Incremental Optimization
Plan

After this stage, you can run post-plan timing analysis to verify timing constraints and validate cross-clock timing windows. View the placement and periphery properties and perform clock planning for Intel® Arria® 10 FPGA and Intel® Cyclone® 10 FPGA designs.
Early Place

After this stage, the Chip Planner can display an initial high-level placement of design elements. Use this information to guide your floorplanning decisions. For Intel® Stratix® 10 FPGA designs, you can also do early clock planning after running this stage.
Place

After this stage, validate the resource and logic utilization in the Compilation Reports and review the placement of design elements in the Chip Planner.
Route

After this stage, perform detailed setup and hold timing closure in the Timing Analyzer and view routing congestions via the Chip Planner.
Retime After this stage, review the Retiming results in the Fitter report and correct any restrictions limiting further retiming optimization.5

By default, the Fitter will run through all its stages. However, you can analyze the results of Fitter stages to evaluate your design before running the next stage, or before running a full compilation. For more information on how to use the Fitter stages to control the quality of results for your design, refer to the Running the Fitter section in volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.

You can specify several settings to direct the effort level of the Fitter for such things as register packing, register duplication and merging, and overall effort level. For more information on Fitter settings, see discussions under the Fitter Settings Reference section in volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.

In the Intel® Quartus® Prime Standard Edition software, you can specify several settings to direct the effort level of the Fitter such as register packing, register duplication and merging, and overall effort level. For a complete listing of Fitter Settings, see Compiler Settings Help Page

For more information on Fitter settings, see discussions under 

The Timing Analyzer determines the timing relationships that must be met for the design to correctly function and checks arrival times against required times to verify timing.

Timing analysis involves many foundational concepts: asynchronous v. synchronous arcs, arrival and required times, setup and hold requirements, etc. These are defined in the Timing Analyzer Terminology and Concepts section in volume 3 of the Intel® Quartus® Prime Standard Edition Handbook.

The Timing Analyzer applies your timing constraints and determines timing delays from the results of the Fitter's implementation of your design into the target device. 

The Timing Analyzer must operate from an accurate description of your timing requirements, expressed as timing constraints. The Constraining Designs section in volume 3 of the Intel® Quartus® Prime Standard Edition Handbook describes how timing constraints can be added to .sdc files, for use by both the Fitter and the Timing Analyzer.

Timing closure is an iterative process of refining timing constraints; adjusting parameters for synthesis and the Fitter, and managing fitter seed variations. 

The Intel Quartus Prime Timing Analyzer

The Timing Analyzer in the Intel® Quartus® Prime software is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry standard constraint, analysis, and reporting methodology. The Timing Analyzer can be driven from a graphical user interface or from a command-line interface to constrain, analyze, and report results for all the timing paths in your design.

A full user guide on the Timing Analyzer can be found in the Running the Timing Analyzer section in volume 3 of the Intel® Quartus® Prime Standard Edition Handbook.

If you are new to Timing Analysis, see the Recommended Flow for First Time Users section in volume 3 of the Intel® Quartus® Prime Standard Edition Handbook. This describes the full design flow using basic constraints.

Timing Analyzer Training Courses

Course Duration Type Course Number
The Intel Quartus Prime Software Design Series: Timing Analysis
8 Hours
Intructor-Led
IDSW120
Advanced Timing Analysis with TimeQuest 8 Hours Instructor-Led IDSW125
Timing Analyzer: Introduction to Timing Analysis 15 Minutes Online, Free ODSW1115
Timing Analyzer: Timing Analyzer GUI 31 Minutes Online, Free ODSW1116
Timing Analyzer: Intel Quartus Prime Integration & Reporting 25 Minutes Online, Free ODSW1117
Timing Analyzer: Required SDC Constraints 34 Minutes Online, Free ODSW1118
Timing Closure Using TimeQuest Custom Reporting 24 Minutes Online, Free OTIM1100

If the Timing Analyzer determines that your timing specifications are not met, then the design must be optimized for timing until the discrepancy is closed and your timing specifications are met.

Timing closure involves several possible techniques. The most effective techniques will vary with each design. The Timing Closure and Optimization chapter in volume 2 of the Intel Quartus Prime Pro Edition Handbook gives a lot of practical advice about the timing closure process.

There are several additional training courses to help you understand how to evaluate your design for the right timing closure techniques.

Timing Closure Training Courses

Course Duration Type Course Number
Incremental Block-Based Compilation in the Intel® Quartus® Prime Pro Software: Timing Closure & Tips 22 Minutes Online, Free OIBBC102
Design Evaluation for Timing Closure 55 Minutes Online, Free ODSWTC02
Best HDL Design Practices for Timing Closure 61 Minutes Online, Free OHDL1130
Timing Closure Using TimeQuest Custom Reporting 24 Minutes Online, Free OTIM1100
Timing Closure with the Quartus® II Software 8 Hours Instructor-Led IDSW145

The Intel® Quartus® Prime and Quartus® II software include a wide range of features to help you optimize your design for area and timing. This section provides the resources to help you with design optimization techniques and tools.

The Intel® Quartus® Prime and Quartus® II software offer physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.

Optimization Support Documentation

Title Description
Area and Timing Optimization This handbook chapter explains how to reduce resource usage, reduce compilation times, and improve timing performance when designing for Intel® devices.
Analyzing and Optimizing the Design Floorplan This handbook chapter describes how to use the Chip Planner to analyze and optimize the floorplan for your designs. This chapter also explains how to use Logic Lock Region to control the placement.
Engineering Change Management with the Chip Planner This handbook chapter describes how to use the Chip Planner to implement engineering change orders (ECOs) for supported devices.
Netlist Optimizations and Physical Synthesis This handbook chapter explains how the netlist optimizations and physical synthesis in Intel® Quartus® Prime software can modify your design’s netlist and help improve the quality of your results.
Incremental Compilation Resource Center

This resource center web page shows how you can use incremental compilation to reduce compilation times and preserve results during optimization.

Design Optimization Training Courses

Course Duration Type Course Number
Using Intel® Quartus® Prime Pro Software: Chip Planner 29 Minutes
Online, Free OPROCHIPPLAN
Using Design Space Explorer  21 Minutes Online, Free ODSE
Timing Closure Using Timequest Custom Reporting 24 Minutes Online, Free OTIM1100
Best HDL Design Practices for Timing Closure 1-hour
Online, Free OHDL1130

The Intel® Quartus® Prime software provides tools that present your design in visual ways. These tools let you diagnose any problem areas in your design, in terms of logical or physical inefficiencies.

  • You can use the Netlist Viewers to see a schematic representation of your design at several stages in the implementation process: before synthesis, after synthesis, and after place-and-route. This enables you to confirm your design intent at each stage.
  • The Design Partition Planner helps you visualize and revine a design's partitioning scheme by showing timing information, relative connectivity densities, and the physical placement of partitions. You can locate partitions in other viewers, or modify or delete partitions.
  • With the Chip Planner, you can make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion. The Design Partition Planner and the Chip Planner allow you to partition and layout your design at a higher level.
  • Design Space Explorer II (DSE) automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.

Using these tools can help you optimize the implementation of the device.

The Intel® Quartus® Prime software netlist viewers provide powerful ways to view your design at various stages. Cross probing is possible with other design views: you can select an item and highlight it in the Chip Planner and Design File Viewer windows.

  • The RTL Viewer shows the logic and connections inferred by the synthesizer, after elaboration of the hierarchy and major logic blocks. You can use the RTL Viewer to check your design visually before simulation or other verification processes.
  • The Technology Map Viewer (Post-Mapping) can help you locate nodes in your netlist after synthesis but before place-and-route. 
  • The Technology Map Viewer (Post-Fitting) shows the netlist after place-and-route. This can differ from the Post-Mapping netlist because the fitter may make optimizations in order to meet constraints during physical optimization.

The RTL Viewer displays the logic inferred by the Synthesis tool after the elaboration of the hierarchy and major functional blocks.

The Technology Map Viewer shows the logic after synthesis (the "post map view") or after placement and routing (the "post fit view").

Netlist and Finite State Machine Viewers

See a demonstration of the Quartus® software Netlist Viewer and Finite State Machine Viewer in the videos below.

Quartus® II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 1)

The Quartus® II RTL Viewer and State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

Quartus® II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 2)

The Quartus® II RTL Viewer and State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

Netlist Viewers Resources

Resource Description
Optimizing the Design Netlist A chapter in the Intel® Quartus® Prime Standard Edition Handbook covering the use of the Netlist Viewers.

Design floorplan analysis helps to close timing and ensure optimal performance in highly complex designs. The  Chip Planner in the Intel® Quartus® Prime software helps you close timing quickly on your designs. You can use the Chip Planner together with Logic Lock Regions to compile your designs hierarchically and assist with floorplanning. Additionally, use partitions to preserve placement and routing results from individual compilation runs.

You can perform design analysis as well as create and optimize the design floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.

Chip Planner Resources

Resource Type Descirption
Analyzing and Optimizing the Design Floorplan Intel® Quartus® Prime Pro Edition Handbook Chapter Primary documentation for Design Floorplan and Chip Planner
Chip Planner Instructional Video (Part 1 of 2) E2E Video Chip Planner tutorial: Cross Reference Timing Paths, Fan-in, Fan-out, Routing Delays, and Clock Regions
Chip Planner Instructional Video (Part 2 of 2) E2E Video
Chip Planner tutorial: Routing Utilization, Design Element Search, and Logic Lock Regions
Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 1 of 3) E2E Video
Making late, small engineering change order (ECO) changes using the Chip Planner
Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 2 of 3)
E2E Video

Making late, small ECO changes using the Chip Planner
Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 3 of 3)
E2E Video

Making late, small ECO changes using the Chip Planner
How to trace the local routing of CDR recovered clock from transceiver channel to I/O pin using the Timing Analyzer and Chip Planner E2E Video An example of how to use the Chip Planner with the Timing Analyzer

Design Space Explorer II (DSE) allows you to explore the many parameters available for design compilation.

You can use the DSE to manage multiple compilations with different parameters to find the best combination of parameters that allow you to achieve timing closure.

Design Space Explorer II Resources

Resource Description
Optimizing with Design Space Explorer II Intel® Quartus® Prime Pro Edition Handbook
Design Space Explorer (DSE) Design Example An example of a design space exploration
Using Design Space Explorer (ODSE) Free online training, 21 minutes

As FPGAs increase in performance, size, and complexity, the verification process can become a critical part of the FPGA design cycle. To alleviate the complexity of the verification process, Intel provides a portfolio of on-chip debugging tools. The on-chip debugging tools allow real-time capture of internal nodes in your design to help you verify your design quickly without the use of external equipment, such as a bench logic analyzer or protocol analyzer. This can alleviate the number of pins needed for board-level signal probing. For a guide to all the tools in the debug portfolio, refer to the System Debugging Tools section in volume 3 of the Intel® Quartus® Prime Pro Edition Handbook.

External memory debugging is facilitated by the Extermal Memory Interface Toolkit, which is detailed in the External Memory Interface Support Center.

The Transceiver Toolkit offers extensive facilities to verify transceiver signal quality and performance. For more information on this toolkit, see the Transceiver Toolkit product page.

On-Chip Debugging Training Courses

Course Duration Type Course Number
SignalTap II Logic Analyzer: Introduction & Getting Started
35 Minutes Online, Free ODSW1164
SignalTap II Logic Analyzer: Basic Trigger Conditions & Configuration
28 Minutes
Online, Free
ODSW1171
SignalTap II Logic Analyzer: Triggering Options, Compilation, & Device Programming
28 Minutes
Online, Free
ODSW1172
SignalTap II Logic Analyzer: Data Acquisition & Additional Features
30 Minutes Online, Free
ODSW1173
The Quartus® Software Debug Tools 8 Hours Instructor-Led IDSW135
Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction 38 Minutes Online, Free OVJTAG1110
Debugging JTAG Chain Integrity 32 Minutes Onilne, Free ODJTAG1110
On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices 32 Minutes Onilne, Free
OMEM1124
System Console
29 Minutes Onilne, Free
OEMB1117
Advanced System Design Using Qsys: System Verification with System Console
25 Mintues Onilne, Free
OAQSYSSYSCON

On-chip Debug - other resources

Resource Description
Altera® Virtual JTAG (altera_virtual_jtag) IP Core User Guide (PDF)

The altera_virtual_jtag Intel® FPGA IP communicates via a JTAG port, allowing you to develop custom debugging solutions.

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (PDF)

Design files (.zip)

Using SignalTap to monitor signals located inside a system module generated by the Platform Designer.


AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer (PDF) This application note examines the use of the Nios® II plug-in within the Signal Tap logic analyzer and presents the capabilities, configuration options, and use-modes for the plug-in.
AN 799: Quick Debugging of Intel® Arria® 10 Designs Using Signal Probe and Rapid Recompile Access internal signals with minimal impact on your design.

The Intel® Quartus® Prime Pro Edition design software offers block-based design flows. There are of two types- the  Incremental Block-Based Compilation and Design Block Reuse flows, which allow your geographically diverse development team to collaborate on a design.

Incremental Block-Based Compilation is preserving or emptying a partition within a project. This works with core partitions and requires no additional files or floor planning. The partition can be emptied, preserved at Source, Synthesis, and Final snapshots.

The Design Block Reuse flow enables you to reuse a block of a design in a different project by creating, preserving, and exporting a partition. With this feature, you can expect a clean hand off of timing-closed modules between different teams.

Block-Based Design Resources

Rapid Recompile allows the reuse of previous synthesis and fitter results when possible, and does not reprocess unchanged design blocks. Rapid Recompile can reduce total compilation time after making small design changes. Rapid Recompile supports HDL-based functional ECO changes and enables you to reduce your compile time while preserving the performance of unchanged logic.

Rapid Recompile - Support Resources

Resource Description
Running Rapid Recompile Rapid Recompile section in volume 2 of the Intel® Quartus® Prime Pro Edition Handbook
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile (PDF) An application note showing how Rapid Recompile reduces the compile time for small changes

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.

You can create multiple personas for a region of your device, and reconfigure that region without impacting operations in areas outside that persona.

For more information on Partial Reconfiguration, see the Partial Reconfiguration page.

The Intel® Quartus® Prime and Quartus® II software includes comprehensive scripting support for command-line and tool command language (Tcl) script design flows. Separate executables for each stage of the software design flow, such as synthesis, fitting, and timing analysis, include options for making common settings and performing common tasks. The Tcl scripting application programming interface (API) includes commands covering basic to advanced functionality. 

Command-Line Scripting

You can use Intel® Quartus® Prime or Quartus® II software command-line executables in batch files, shell scripts, makefiles, and other scripts. For instance, use the following command to compile an existing project:

        $ quartus_sh --flow compile

Tcl Scripting

Use the Tcl API for any of the following tasks:

  • Creating and managing projects
  • Making assignments
  • Compiling designs
  • Extracting report data
  • Performing timing analysis

You can get started with some of the examples in the Quartus® II software Tcl examples web page. Several other resources are listed below.

Scripting Resources

Resource Description
Quartus® II Scripting Reference Manual Covers both Quartus® software command-line executables and Tcl packages and commands from within a  Quartus® software shell
Quartus® Prime Standard Edition Settings File Reference Manual Covers parameter settings found in the Quartus® software Settings File (.qsf).
Command Line Scripting
A chapter of the Intel Quartus Prime Handbook.
Quartus® II Tcl Examples A web page with several useful Tcl script examples.
Command Line Scripting (ODSW1197) Online training presenting the command line scripting  capabilities in the Intel® Quartus® software (30 min).
Introduction to Tcl (ODSW1180) An Introduction to the Tcl scripting syntax.
Quartus® II Software Tcl Scripting (ODSW1190) Tcl Scripting capabilities in the Quartus® II software.

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