Intel® FPGA IP for Transceiver PHY – Support Center

Welcome to the Intel® FPGA intellectual property (IP) for Transceiver PHY support center! 

Here you will find information on how to select, design, and implement transceiver links. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish.  

Enjoy your journey!

Table 1 - Device Variant and Feature Support
Device Intel® Arria® 10 Intel® Stratix® 10
Device Variant SX(3) GX(3) GT(4) GX/SX L-Tile GX/SX H-Tile
Maximum Data Rate (Chip-to-Chip)(1)(7)

GX channels  - 1.0(2) Gbps to 17.4 Gbps

No GT channels available

GX channels  - 1.0 Gbps to 17.4 Gbps

GT channels – 1.0 Gbps to 25.8 Gbps

GX (5)— 1.0  Gbps(2)  to 17.4 Gbps

GXT (5)—1.0 Gbps to 26.6 Gbps

GX (5)— 1.0 Gbps to 17.4 Gbps

GXT (5)—1.0 Gbps to 28.3 Gbps

Maximum Data Rate (Backplane) (8)

GX channels 1.0 Gbps to 12.5 Gbps

No GT channels available

GX and GT channels 1.0 Gbps to 12.5 Gbps GX and GXT –1.0 Gbps to  12.5 Gbps GX and GXT – 1.0 Gbps to 28.3 Gbps
Maximum Channels 96 GX channels/device 72 transceiver channels (up to 6 GT channels/device) 96 GX channels/ device 32 GXT channels/ device (8 per tile) 96 GX channels/device 64 GXT channels/ device (16 per tile)
Hard IP PCIe* Gen3 x8 up to 4 per device PCIe Gen3 x16 up to 4 per device 50/100 Gbps Ethernet MAC up to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF) (6)
PHY IP Core(s) Respective device and tile-related Transceiver Native PHY IP Cores, ATX phase-locked loop (PLL) IP Core, fractional PLL IP Core, CMU PLL IP Core, and Transceiver PHY Reset Controller. For example: Use the Intel® Stratix® 10 device (L-/H-Tile) Transceiver PHY Native PHY IP core for the Intel® Stratix® 10 GX/SX L-Tile and H-Tile devices.
Notes:
  1. The values shown in the table above are for standard power modes. In reduced power mode, the maximum data rate for Intel® Arria® 10 GX device channels (chip-to-chip) is 11.3 Gbps. As the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. For more details, refer to the Intel® Arria® 10 Device Datasheet.
  2. Intel® Arria® 10 and Intel® Stratix® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
  3. For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade.
  4. For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade.
  5. Intel® Stratix® 10 device transceivers have both GX and GXT types of transceiver channels. For details, refer to the Intel® Stratix® 10 L-/H-Tile Transceiver PHY User Guide.
  6. SR-IOV stands for Single-Root Input Output Virtualization.
  7. Intel® Arria® 10 and Intel® Stratix® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
  8. Backplane applications refer to the ones that require advanced equalization, such as decision feedback equalization (DFE) enabled to compensate for channel loss.
Refer to the Overview chapter of the following user guides:
 
Intel® Arria® 10 Devices
Intel Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

  • Intel® Stratix® 10 GX, MX, and SX Schematic Review Worksheet - coming soon
Title Description
Intel® Arria® 10 Device Configuration of a Simplex Transceiver Watch this video to learn how to place an Intel® Arria® 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel.
Dynamic Reconfiguration of an Intel® Arria® 10 Device Transceiver Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Intel® Arria® 10 devices.
How to Use the Transceiver Toolkit Part 1 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver.
How to Use the Transceiver Toolkit Part 2 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 3 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 4 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
Intel® Arria® 10 Transceivers: Pre-Emphasis Basics Learn the basics of the Intel® Arria® 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements.
Performing Dynamic Reconfiguration for the Intel® Arria® 10 Device Transceiver Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Intel® Arria® 10 devices.
Reconfigure Intel® Arria®10 Device Transceivers Using Embedded Streamer Watch this video to learn  how to perform dynamic reconfiguration with the Intel® Arria® 10 device transceiver Standard PCS using the embedded streamer.
Use the IBIS-AMI Model to Estimate Signal Integrity of Intel® Arria® 10 Device Transceiver Watch this video to learn how to perform a signal integrity simulation with the Intel® Arria® 10 device transceiver IBIS-AMI model in the Intel® Advanced Link Analyzer. Additionally, this video covers eye diagram reporting.

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