Course DescriptionAs FPGA designs become more complex, a larger part of development time is spent verifying designs. This course introduces the various debug tools included in the Quartus® Prime software v. 16.1 & shows effective ways to debug an FPGA design, decreasing overall design development time. The class discusses various debugging tools: the SignalTap® II embedded logic analyzer (ELA), SignalProbe, In-System Sources & Probes, the Logic Analyzer Interface, System Console, Chip Planner and others. The focus is on the SignalTap II ELA, including hands-on lab exercises utilizing the tools on real designs.
At Course Completion
You will be able to:
- Debug designs in-system using the SignalTap II embedded logic analyzer
- Quickly route internal nodes to unused I/O pins without performing a full recompilation using SignalProbe incremental routing
- View & edit embedded memory contents using In-System Memory Content Editor
- View compilation results & make incremental design changes with Chip Planner
- Connect internal debug nodes to an external logic analyzer using Logic Analyzer Interface
- Debug a Qsys system using System Console
- Completion of "The Quartus Software Design Series: Foundation" course OR a working knowledge of the Quartus software
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
No class is being offered at this time.