Design Optimization Using Quartus II Incremental Compilation (IDSW142)

8 Hours Instructor-Led / Virtual Class Course

Course Description

Debugging and optimizing a large FPGA design can be difficult and time consuming. Every change made to fix a problem or to help close timing requires the design to be completely recompiled. Not only can this take a long time, but the performance of untouched parts of the design can be affected. Integrating the work of different members on a team into a single design only adds to the complexity. In this class, you will learn how to use the incremental compilation feature and LogicLock regions in the Quartus® II software to help reduce compile times, preserve performance, and close timing. You’ll see how the tools in the Quartus II software make it easy to follow an incremental design flow that will help you finish your design cycles sooner.

At Course Completion

You will be able to:

  • Set up and perform incremental compilation through design partition creation and floorplanning in the Quartus II software
  • Understand the advantages and disadvantages of incremental compilation
  • Create good design partitions by following best practices
  • Lock performance of sub-designs by reusing previously compiled netlists
  • Close timing using incremental compilation
  • Apply incremental compilation to single-project and multi-project (team-based) design flows

Skills Required

  • Experience with PCs and the Windows operating system
  • Completion of "The Quartus II Software Design Series: Foundation" course OR a working knowledge of the Quartus II software
  • Completion of “The Quartus II Sotware Design Series: Timing Analysis” course OR a working knowledge of Synopsys Design Constraints (SDC) and the TimeQuest timing analyzer

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

No class is being offered at this time.