Course DescriptionThis class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of the Verilog module, data types, operators and assignment statements needed to begin creating your own designs, using both behavioral and structural approaches. In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing simple but practical designs. You will check your designs by compiling in the Quartus® II software version 10.1 and simulating in the ModelSim®-Altera® tool.
At Course Completion
You will be able to:
- Create a basic Verilog module
- Understand the difference between simulation and synthesis environments
- Understand Verilog data types and operators and their uses
- Model hardware and test using behavioral modeling constructs
- Model hardware and test using structural modeling constructs
- Background in digital logic design
- Knowledge of simulation is a plus
- Prior knowledge of a programming language (e.g., "C" language) is a plus
- No prior knowledge of Verilog HDL or the Quartus II software is needed
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
No class is being offered at this time.