Course DescriptionIn this class, you will learn about the Partial Reconfiguration (PR) capabilities of Altera® FPGAs. Starting in Altera 28 nm devices, you are able to change the functionality of a portion of an active FPGA, while the rest of the FPGA operates uninterruptedly. During this training, you will explore the benefits and limitations of PR, understand the design guidelines involving PR, and learn the steps necessary to enable this feature. During the exercises, you will prepare a design for PR using the Quartus® II software v. 13.0, complete the design of a PR controller, and test the feature on a development board.
At Course Completion
You will be able to:
- Understand the Partial Reconfiguration design flow
- Prepare a design for Partial Reconfiguration
- Design and instantiate a Partial Reconfiguration controller
- Create partial configuration files
- Partially reconfigure a running FPGA design
- Understand the limitations of Partial Reconfiguration
- Completion of "The Quartus II Software Design Series: Foundation" course OR a working knowledge of the Quartus II software
- Knowledge of a Hardware Description Language
- Completion of "Design Optimization Using Quartus II Incremental Compilation" course OR a working knowledge of incremental compilation
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.