Partial Reconfiguration with Arria 10 FPGAs (IPR200)

8 Hours Instructor-Led / Virtual Class Course

Course Description

One advantage of an FPGA is the ability to change its function through reconfiguration. This normally replaces the entire FPGA design. What if you could reconfigure just part of the overall design, replacing blocks with different functionality while the main design is still running? In this class, you'll learn how to implement Partial Reconfiguration (PR) in an Intel® FPGA. Focusing on 20 nm Arria 10 devices, you'll know how to change the functionality of a portion of the device, while the rest operates without interruption. Explore the benefits and limitations of PR, understand design guidelines, and learn the steps to enable this feature. Through lab exercises, you will prepare a design for PR using the Quartus® Prime Pro software, complete the design, and test the feature on a board.

At Course Completion

You will be able to:

  • Understand the Partial Reconfiguration design flow
  • Prepare a design for Partial Reconfiguration
  • Design or instantiate a Partial Reconfiguration host controller
  • Generate required partial reconfiguration programming files through design compilation
  • Debug a partial reconfiguration design
  • Understand the limitations of Partial Reconfiguration

Skills Required

  • Completion of "The Quartus Prime Software: Foundation" course OR a working knowledge of the Quartus Prime software
  • Knowledge of a Hardware Description Language (Verilog or VHDL)

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

No class is being offered at this time.