Are you targeting a Stratix® 10 device and want to learn how your design can reach the maximum core performance?
In this course, you'll learn design techniques to enable you to unleash the full potential of the Stratix 10 HyperFlex™ architecture using Hyper-Optimization. You will learn how to identify logic structures that are limiting retiming and thus design performance. You will then learn how to modify your coding style and logic structures and, as a result, allow your design to achieve clock rates of up to 2 times compared to a non-optimized design, without changing overall design functionality.
Note: While the focus of this course is the Stratix 10 device family, many techniques you will learn can be used to improve performance in other device architectures.
At Course Completion
You will be able to:
- Learn to interpret complex retiming reports to locate & understand critical chains, design paths requiring further optimization for improved performance
- Learn Hyper-Optimization techniques to restructure design logic to take advantage of the Stratix 10 HyperFlex architecture (or any FPGA architecture) using techniques such as 1) Unrolling loops, 2) Pre-computation to reduce loop size, 3) Shannon’s Decomposition, 4) Time-domain multiplexing retiming, 5) Hyper-Folding, and 6) Loop pipelining
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus® Prime Pro Edition design software
- Familiarity with Verilog or VHDL synthesizable design structures
- Completion of the “Performance Optimzation with Stratix 10 HyperFlex Architecture” course
We recommend completing the following courses:
- Performance Optimization with Stratix 10 HyperFlex Architecture
- The Quartus Prime Software: Foundation (Instructor-led / Virtual Training)
- The Quartus Prime Software: Foundation (Standard Edition) (Online Training)
- The Quartus® Prime Software Design Series: Timing Analysis
- TimeQuest Timing Analyzer: Introduction to Timing Analysis
- Timing Closure with the Quartus II Software
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: