Performance Optimization with Stratix 10 HyperFlex Architecture (IS10PERF)

8 Hours Instructor-Led / Virtual Class Course

Course Description

In the Performance Optimization with Stratix® 10 HyperFlex™ Architecture course, you will learn Intel® Quartus® Prime Pro software features and some basic design techniques that will enable your designs to take advantage of the Stratix 10 HyperFlex architecture. In the training, you will learn two steps to improving your performance with the HyperFlex architecture, namely Hyper-Retiming and Hyper-Pipelining, with each step allowing you to move your design up the performance curve.

Note: While the focus of this course is the Stratix 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures.

At Course Completion

You will be able to:

  • Describe the Stratix 10 device architecture, including the new HyperFlex architecture
  • Enable the Quartus software features that take advantage of the HyperFlex architecture
  • Evaluate possible design improvements using the Quartus software’s Fast Forward Compile feature
  • Improve your Stratix 10 design performance by understanding and enabling Hyper-Retiming
  • Improve your Stratix 10 design performance by implementing zero-latency Hyper-Pipelining

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus design software
  • Familiarity with Verilog or VHDL synthesizable design structures

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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Virtual Classroom03/06/2018 - 03/07/2018$695Register Now
Virtual Classroom05/08/2018 - 05/09/2018$695Register Now