Building Gigabit Interfaces in 28-nm Devices (ITRNSCVR)

8 Hours Instructor-Led Only Course

Course Description

In this course, you will learn how you can build high-speed, gigabit interfaces using the 28-nm embedded transceivers found in Cyclone® V, Arria® V and Stratix® V FPGA families. You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration controller and how you can use it to fine tune transceiver settings and add flexibility to your transceiver design. Lastly, you will be made aware of common “gotchas” that occur in transceiver designs and what steps you can take to avoid them. This course uses the Quartus® II software v. 13.1.

At Course Completion

You will be able to:

  • Implement high-speed serial protocols in Altera® 28-nm embedded transceivers
  • Optimize analog settings to improve link behavior using Altera tools
  • Employ transceiver reconfiguration to dynamically change transceiver behavior in-system
  • Improve transceiver usage and avoid transceiver design issues by applying an understanding of device architecture to design situations

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus II design software
  • Familiarity with FPGA architecture
  • Familiarity with high-speed interfaces and transmission protocols is helpful, but not required

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

No class is being offered at this time.