This course will instruct you in how to configure the high-speed PHY layer found in Cyclone® IV, Arria II®, Stratix IV and HardCopy® IV devices for a custom protocol implementation.You will learn the signals available to enable data transfers at rates up to and over 10 Gbps. You will learn how to use the Quartus II software version 10.1 to configure the transceivers and generate design logic to hook up to your own higher layer functional blocks. If you choose, you may download exercise instructions to practice developing and verifying a custom protocol solution.
For designs targeting Cyclone V, Arria V and Stratix V devices, please see the online training Custom Protocol Design in Altera 28-nm Devices.
At Course Completion
You will be able to:
- Describe the features of the Altera transceivers
- Interface a custom serial protocol solution to embedded transceivers
- Use the ALTGX MegaWizard plug-in to configure a custom PCS and PHY solution
- Verify in simulation a design using the ALTGX megafunction
- Familiarity with common high-speed transceiver architecture OR completion of the online course Transceiver Basics
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus II design software
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Altera training curriculum: