Timing Analyzer: Required SDC Constraints (ODSW1118)

34 Minutes Online Course

Course Description

This training is part 4 of 4. Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. The Timing Analyzer, part of the Intel® Quartus® Prime software, is an easy-to-use tool for creating Synopsys® design constraints (SDC) files and for generating detailed timing reports to shorten the process of timing closure. This final part of the training discusses the SDC constraints required to fully constrain a design. While all paths in a design need to be constrained, you'll learn how to constrain clock and I/O paths, the minimum constraints required for the tool to consider a design to be fully constrained. You'll also learn how to adjust how a timing analysis is performed through the use of clock latency, uncertainty, and timing exceptions.

At Course Completion

You will be able to:

  • Create the constraints required to fully constrain a design, including clocks and I/O
  • Learn about additional constraints that adjust the way timing analysis is performed to match the design's operation

Skills Required

  • Background in digital logic design
  • An understanding of basic FPGA design flow
  • A solid working knowledge of the Intel Quartus Prime software

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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