SignalTap II Logic Analyzer: Triggering Options, Compilation, & Device Programming (ODSW1172)

28 Minutes Online Course

Course Description

This training is part 3 of 4. The SignalTap® II embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training discusses the sequential and state-based triggering flows and how to configure each. It also describes the process of compiling a project that includes a SignalTap II logic analyzer, run-time reconfigurable options, and how to program a device in preparation for data acquisition and analysis.

At Course Completion

You will be able to:

  • Understand the differences between the sequential and state-based triggering flows
  • Set up a state-based triggering flow state machine
  • Compile a project that includes a SignalTap II logic analyzer
  • Perform a Rapid Recompile to save compile time when adding, deleting, or changing SignalTap nodes

Skills Required

  • Basic knowledge of the Quartus Prime software
  • Knowledge of external logic analyzer operations (optional)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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