Course DescriptionThis presentation describes good practices for designing high-speed core logic in Altera FPGAs. As bandwidth rises and time to market pressures increase, it’s more critical to use good design practices to ensure a quick design and timing closure cycle. The techniques are useful even if your design runs at low or medium speeds. If you follow these design techniques, the design will be easier to close timing, regardless of the clock frequency it runs at. It will also have shorter compile times.
At Course Completion
You will be able to:
- Understand the mindset you should have as a designer to get the best results
- Employ pipelining
- Reduce logic depth
- Understand tradeoffs with bus width and speed
- Be aware of how physical implementation affects performance
- Manage high fanout
- Employ flow control techniques.
- An understanding of basic FPGA design flow
- Familiarity with VHDL or Verilog HDL
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: