Course DescriptionIn this training you will learn about Hard Processor Subsystem (HPS) in the Cyclone® V, Arria® V, and Arria 10 SoCs. The online training includes information about the MPU subsystem, including the ARM® Cortex™-A9 processor core. Various components of the MPU subsystem such as the processor, co-processors, interrupt controller, and caches will be discussed.
At Course Completion
You will be able to:
- Understand the MPU subsystem and Cortex-A9 processor core as implemented in Altera SoCs
- Basic knowledge of FPGA architecture
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: