SoC Hardware Overview: the Microprocessor Unit (OEMB5500)

34 Minutes Online Course

Course Description

In this training you will learn about Hard Processor Subsystem (HPS) in the Cyclone® V, Arria® V, and Arria 10 SoCs. The online training includes information about the MPU subsystem, including the ARM® Cortex™-A9 processor core. Various components of the MPU subsystem such as the processor, co-processors, interrupt controller, and caches will be discussed.

At Course Completion

You will be able to:

  • Understand the MPU subsystem and Cortex-A9 processor core as implemented in Altera SoCs

Skills Required

  • Basic knowledge of FPGA architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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