High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: Introduction, Architecture (OHBMS10)

30 Minutes Online Course

Course Description

High Bandwidth Memory, or HBM, is the next generation of high-speed memory built into Intel® Stratix® 10 MX FPGA devices using System in Package (SiP) technology. HBM2 enables the highest levels of bandwidth not feasible with other solutions. Multiple DRAM layers are connected to a base I/O layer to form a 3-D, high-speed memory connected to and controlled directly by hard memory controllers built into the Intel Stratix 10 MX device. Integrating HBM directly in the FPGA package reduces board size and cost, simplifies and reduces power requirements, and makes it easy to add to your Intel Quartus® Prime Pro Edition project. This part of the training is an introduction to HBM and its architectural implementation in Intel Stratix 10 MX devices.

At Course Completion

You will be able to:

  • Understand the benefits of using the High Bandwidth Memory (HBM) integrated into Intel® Stratix® 10 MX FPGA devices
  • Know about the features of and options for the hardened HBM controller
  • Create an implementation of the HBM interface and controller in the Intel Quartus® Prime Pro edition software

Skills Required

  • Basic knowledge of the Intel® Quartus® Prime software
  • Familiarity with external memory and related interfaces
  • Familiarity with the Arm AMBA 4 AXI interface standard

Prerequisites

We recommend completing the following courses:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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