Incremental Block-Based Compilation in the Intel Quartus® Prime Pro Software: Timing Closure & Tips (OIBBC102)

22 Minutes Online Course

Course Description

This training is part 3 of 3. Designing, organizing, and optimizing a large FPGA design can be difficult and time consuming. Every change made to fix a problem or to help close timing requires the design to be completely recompiled. Not only can this take a long time, but the placement and routing of untouched parts of the design can be affected. In this training, you will learn about incremental block-based compilation, the ability to partition your design and choose which parts should be reused in subsequent compilations. This feature will help you reduce compile times, preserve performance, and close timing faster. This final part of the training provides some general tips & techniques as well as a methodology for using the feature to close timing.

At Course Completion

You will be able to:

  • Set up and perform incremental block-based compilation through design partition creation in the Quartus® Prime Pro Edition software
  • Understand the different design flows (top-down, bottom-up) for implementing a block-based design
  • Preserve compiled design partitions by reusing previous compilation results in a single project

Skills Required

  • Basic knowledge of the Intel Quartus Prime software
  • Knowledge of creating FPGA designs in a hardware description language (Verilog or VHDL)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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