Initial Design Review for Arria® 10 SoC FPGA Designs (OIDR100)

28 Minutes Online Course

Course Description

In this training, you will learn a general process for conducting an initial design review for any FPGA design. Then, we will explore the areas for review for an Arria® 10 SoC FPGA design: HPS Design, Board Design, and Embedded Software Design. The course will follow the checklists and advice offered in the Arria 10 SoC Device Design Guidelines document. Each discussion of a subject area for review will include 3 sections: reference documents, design considerations, and deliverables and actions.

At Course Completion

You will be able to:

  • Describe a general process for conducting an initial design review
  • Describe the Arria® 10 SoC FPGA design considerations that should be reviewed
  • Name the deliverables that should be expected from each team member

Skills Required

  • Familiarity with the basic architecture of a SoC FPGA

Prerequisites

We recommend completing the following courses:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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