Creating Reusable Design Blocks: Introduction to IP Reuse (OIPR1000)

25 Minutes Online Course

Course Description

This training is part 1 of 3. As FPGA designs get larger and more complicated, intellectual property (IP) is being used more often to help reduce time-to-market. Including IP allows designers to focus on new aspects of their design and improve existing designs instead of spending time recreating what’s been done before. But what if you want to create your own IP? This training is for the IP designer who wants to create good quality, easily reusable IP based on Altera’s own methodology for designing reusable IP for use in the Quartus® II software.

At Course Completion

You will be able to:

  • Recognize the benefits of reusing existing IP and complete designs
  • Understand what is required to create good reusable IP

Skills Required

  • Background in digital logic design
  • Familiarity with an HDL language (Verilog or VHDL)
  • Familiarity with the Quartus II software
  • Familiarity with Tcl scripting
  • Some familiarity with SDC timing constraints

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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