Integrating an Analog to Digital Converter in Intel® MAX® 10 Devices (OMAXADC102)

24 Minutes Online Course

Course Description

This training is part 2 of 3. The Intel® MAX® 10 device family consists of Intel FPGA's smallest, low-cost, instant-on programmable logic devices. Besides support for the Nios® II embedded soft processor and connections to high performance external memory, most Intel MAX 10 devices feature an integrated analog-to-digital converter (ADC) block. This part of the training discusses how to use the IP Parameter Editor to parameterize the ADC and how to integrate the generated IP into a design.

At Course Completion

You will be able to:

  • Understand the basic architecture and features of the analog to digital converter (ADC) IP found in Intel® MAX® 10 devices
  • Implement the Intel MAX 10 ADC hard IP in an FPGA design
  • Monitor analog inputs using the ADC Toolkit

Skills Required

  • Background in digital logic design
  • Familiarity with the Intel® Quartus® Prime software
  • Familiarity with the Platform Designer system design tool

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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