Introduction to Memory Interfaces IP in Arria 10 & Stratix 10 Devices (OMEM1121)

41 Minutes Online Course

Course Description

This training is part 1 of 4. Altera's new Arria® 10 and Stratix® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps. This part of the training introduces the memory options available and describes how the architecture makes such performance possible. It also describes the unique features of the built-in hard memory controller needed to achieve such speeds.

At Course Completion

You will be able to:

  • Know the external memory interface (EMIF) options available in Arria 10 and Stratix 10 devices
  • Understand the new architectural features for implementing memory interfaces
  • Learn about the features of the new hard memory controller that make higher speed interfaces possible

Skills Required

  • Background in digital logic design
  • Basic knowledge of memory interfaces
  • Familiarity with the Quartus II software
  • Familiarity with memory interfaces in Altera devices from either of the listed prerequisite training classes

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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