Verifying Memory Interfaces IP in Arria 10 Devices (OMEM1123)

27 Minutes Online Course

Course Description

This training is part 3 of 4. Altera's new Generation 10 devices, including Arria® 10 and Stratix® 10 devices, introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.6 Gbps. This part of the training discusses how to perform a simulation of the altera_emif IP either by itself or using the generated example design. When generated, the IP creates all the files needed to perform a simulation. Timing analysis of the IP is also discussed along with suggestions for timing closure. The hard resources used for altera_emif along with easier-to-read timing reports simplifies analysis and closure.

At Course Completion

You will be able to:

  • Verify the functionality of a Generation 10 EMIF design through simulation
  • Perform a normal timing analysis or use the new early I/O timing analysis

Skills Required

  • Background in digital logic design
  • Basic knowledge of memory interfaces
  • Familiarity with the Quartus II software
  • Familiarity with memory interfaces in Altera devices from the listed prerequisite training classes

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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