On-Chip Debugging of Memory Interfaces IP in Arria 10 Devices (OMEM1124)

32 Minutes Online Course

Course Description

This training is part 4 of 4. Altera's new Generation 10 devices, including Arria® 10 and Stratix® 10 devices, introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.6 Gbps. This part of the training discusses the use of the EMIF Debug Toolkit, the On-Chip Debug Port, and the new Traffic Generator 2.0 IP. As on previous device families, these tools provide runtime information through a JTAG connection or through software control on the calibration and available margin in a memory interface. Due to the changes in the Generation 10 memory architecture from previous devices, this training also discusses the system design changes required to use these tools with designs that include multiple memory interfaces.

At Course Completion

You will be able to:

  • Perform on-chip debugging of an Arria 10 memory interface using the EMIF Toolkit or the On-Chip Debug Toolkit
  • Learn how to use the Traffic Generator 2.0 IP to send customized test traffic patterns to the external memory
  • Configure a design with multiple memory interfaces to work with these tools

Skills Required

  • Background in digital logic design
  • Basic knowledge of memory interfaces
  • Familiarity with the Quartus Prime software
  • Familiarity with memory interfaces in Altera devices from the listed prerequisite training classes

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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