Stratix® 10 HyperFlex™ Architecture Overview (OS10ARCH)

26 Minutes Online Course

Course Description

In the Stratix® 10 HyperFlex™ Architecture Overview course, you will learn the new architectural advancements made to Intel® Stratix 10 FPGAs that enable designs to run at speeds up to 2X, on average, when compared to conventional FPGA architectures. You will learn about the Hyper-Register, the basic building block of the HyperFlex architecture, and receive an overview of the three design techniques for taking advantage of Hyper-Registers, namely Hyper-Retiming, Hyper-Pipelining and Hyper-Optimization.

At Course Completion

You will be able to:

  • Describe the Intel® Stratix® 10 HyperFlex™ architecture, including: Hyper-Registers and Programmable Clock Tree Synthesis
  • Define Hyper-Retiming, Hyper-Pipelining and Hyper-Optimization, the three techniques to achieve 2X or more performance gains for improving design performance in Stratix 10 devices

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with FPGA architecture

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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