Introduction to Hyper-Retiming (OS10IHYPRET)

18 Minutes Online Course

Course Description

In the Introduction to Hyper-Retiming course, you will learn how to employ Hyper-Retiming, the first of three steps to improving your design’s performance with the HyperFlex™ architecture, with each step allowing you to move up the performance curve. This course will show you how Hyper-Retiming works and the advantages Hyper-Retiming has over traditional forms of retiming used in conventional FPGA architectures today.

Note: While the focus of this course is the Stratix® 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures.

At Course Completion

You will be able to:

  • Define how Hyper-Retiming differs from conventional retiming
  • Enable Hyper-Retiming in your Quartus II project
  • Describe how Hyper-Retiming works in a Stratix 10 device

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus® II design software
  • Familiarity with Verilog or VHDL synthesizable design structures

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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