In the SEU Mitigation in Intel® FPGA Devices: Hierarchy Tagging training, you will learn how you can improve your sensitivity processing solution by supplementing this single event upset (SEU) mitigation technique with another Intel® Stratix® 10, Intel Arria® 10, Intel Cyclone® 10 GX & Intel Quartus® Prime Pro feature called hierarchy tagging. The result can be significantly less FPGA down time when an error caused by SEU occurs. You will understand how hierarchy tagging works, how to enable it in your FPGA design & how to use it when designing an SEU recovery solution.
Though the class focuses on the Intel Stratix 10, Intel Arria 10 and Intel Cyclone 10 GX families, some techniques are supported on select older device families. Please see your device user guide.
At Course Completion
You will be able to:
- Define hierarchy tagging and how it can improve a single event upset (SEU) mitigation solution
- Enable hierarchy tagging and assign sensitivity IDs in the Intel® Quartus® Prime Pro software
- Implement control logic that uses hierarchy tags to filter responses to SEU
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel® Quartus® Prime Pro design software
We recommend completing the following courses:
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: