Mitigating Single Event Upsets in Intel® Arria® 10 and Intel Cyclone® 10 GX Devices (OSEUMTGTN)

23 Minutes Online Course

Course Description

As cloud-based services continue to grow, protection of that cloud data is even more important, such that single event upsets (SEU) are not just the concern of avionics and safety critical systems. With that in mind, this online training serves as the starting point in understanding Intel FPGA solutions to detecting, correcting and managing SEU events.

In this training, you will start with a brief introduction to SEU and its terms. You then learn the features of the Intel Arria 10 and Intel Cyclone 10 GX device families that can be used in the designing your own SEU mitigation solution. Finally, you will investigate the Advanced SEU Detection (ASD) IP Core to see how you can use this core to even further fine tune your SEU detection and response.

At Course Completion

You will be able to:

  • Enable Intel Arria 10 and Intel Cyclone 10 GX device features to reduce your Failures in Time (FIT) rate and to develop a SEU fault response solution
  • Employ the Advanced SEU Detection (ASD) IP core to improve your fault response by filtering SEU events

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Intel Quartus® Prime design software

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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