Timing Closure Using TimeQuest Custom Reporting (OTIM1100)

24 Minutes Online Course

Course Description

Learn how to use the Quartus® II v. 10.1 Timing Closure Recommendations reporting in the TimeQuest Timing Analyzer to help you find issues that may be causing timing failures.

At Course Completion

You will be able to:

  • Use the Timing Closure Recommendation custom reporting feature in TimeQuest to close timing on your designs
  • Identify HDL code changes needed to address timing issues
  • Change Quartus II software settings to address timing issues

Skills Required

  • Background in digital logic design
  • Basic understanding of Verilog or VHDL coding
  • An understanding of basic FPGA design flow
  • Basic understanding of the Quartus II user interface
  • Basic understanding of the TimeQuest timing analyzer

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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