Intel FPGA Curricula Introduction

The table below shows the curriculum flow for each of the specialties listed on the menu to the left.   Software engineers may  proceed directly to the courses listed in the Software Development curriculum.  Hardware engineers should first review the courses listed under the Fundamentals Part 1 and Part 2 category and take any that are unfamiliar before moving on to the courses listed under their specialty.

 

The flowchart below gives you an overview of all instructor-led and virtual courses. The foundation (fundamental) courses are shown at the top. The advanced follow-on courses are shown just below the foundation courses. Specialized courses are shown at the bottom. Any course with a dotted line around it indicates that it is available as either an instructor-led class or as a virtual class. If there is no dotted line around a course then it is only available as an instructor-led course. The arrows show you the order we recommend some of the courses to be taken.

Note - free online versions of the Quartus Software Foundation course are available here.

curricula-flowchart

Intel FPGA Fundamentals Part 1

Recommended Courses

These courses cover the basics of programmable logic design including FPGA design using VHDL or Verilog HDL.  Learn how to set up and use the Quartus software to create and run basic FPGA designs. 

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  Read Me First! Online 46 Minutes English
  Altera产品和资源入门指南 (Chinese Version of Read Me First! ) Online 26 Minutes Chinese
  アルテラ・サイト ご利用ガイド (Japanese Version of Read Me First) Online 50 Minutes Japanese
  Become a FPGA Designer in 4 Hours Online 4 Hours English
  Basics of Programmable Logic: History of Digital Logic Design Online 21 Minutes English
  Basics of Programmable Logic: FPGA Architecture Online 34 Minutes English
  可编程逻辑基础:数字逻辑设计的历史 (Chinese Version: Basics of Programmable Logic: History of Digital Logic Design) Online 24 Minutes Chinese
  可编程逻辑基础:FPGA架构 (Chinese Version: Basics of Programmable Logic: FPGA Architecture) Online 33 Minutes Chinese
  プログラマブル・ロジックの基礎: デジタル・ロジック・デザインの歴史 (Japanese Basics: History of Digital Logic Design) Online 32 Minutes Japanese
  プログラマブル・ロジックの基礎: FPGA アーキテクチャ (Japanese Version: Basics of Programmable Logic: FPGA Architecture) Online 57 Minutes Japanese
  How to Begin a Simple FPGA Design Online 19 Minutes English
  如何开始一个简单的FPGA设计 (Chinese Version of How to Begin a Simple FPGA Design) Online 14 Minutes Chinese
  はじめてのFPGA設計 (Japanese Version of How to Begin a Simple FPGA Design) Online 21 Minutes Japanese
  Introduction to Verilog HDL Instructor-Led / Virtual Class 8 Hours English
Verilog HDL Basics Online 50 Minutes English
Verilog HDL基础 (Chinese Version of Verilog HDL Basics) Online 39 Minutes Chinese
Verilog HDL 基礎編 (Japanese Version of Verilog HDL Basics) Online 49 Minutes Japanese
  Introduction to VHDL Instructor-Led / Virtual Class 8 Hours English
  Getting Started with VHDL (Europe) Instructor-Led Only 16 Hours German
VHDL Basics Online 92 Minutes English
VHDL基础 (Chinese Version of VHDL Basics) Online 45 Minutes Chinese
VHDL 基礎編 (Japanese Version of VHDL Basics) Online 68 Minutes Japanese
  The Quartus Prime Software: Foundation (Instructor-led / Virtual Training) Instructor-Led / Virtual Class 8 Hours English
  Quartus II パーフェクト・コース I (Foundations) Instructor-Led Only 8 Hours Japanese
  The Quartus Prime Software: Foundation (Standard Edition) (Online Training) Online 8 Hours English
  The Quartus Prime Software: Foundation (Pro Edition) (Online Training) Online 8 Hours English
Quartus II 软件设计系列:基础 (Chinese Version of The Quartus II Software Design Series: Foundation) Online 8 Hours Chinese
Using the Quartus Prime Software: An Introduction Online 81 Minutes English
使用Quartus Prime 软件工具: 简介 (Chinese Version of Using the Quartus Prime Software: An Introduction) Online 68 Minutes Chinese
Quartus II開発ソフトウェア 基礎編:スタート・ガイド (Japanese Version of Quartus II Foundation: Getting Started) Online 47 Minutes Japanese
Quartus IIパーフェクト・コース:I/O プランニング (Japanese Version of Quartus II Foundation: I/O Planning) Online 33 Minutes Japanese
Quartus IIパーフェクト・コース:コンパイル (Japanese Version of Quartus II Foundation: Compilation) Online 33 Minutes Japanese
Quartus IIパーフェクト・コース:デザイン入力 (Japanese Version of Quartus II Foundation: Design Entry) Online 35 Minutes Japanese
Quartus IIパーフェクト・コース:プログラミングとコンフィギュレーション (Japanese Quartus II Foundation: Programming/Configure) Online 13 Minutes Japanese
Quartus IIパーフェクト・コース:設定とアサインメント (Japanese Version Quartus II Foundation: Settings Assignments) Online 24 Minutes Japanese
Introduction to Configuring Altera FPGAs Online 19 Minutes English
配置Altera FPGA的介绍 (Chinese Version of Introduction to Configuring Altera FPGAs) Online 20 Minutes Chinese
Configuration Schemes for Altera FPGAs Online 21 Minutes English
Altera FPGA器件的配置方案 (Chinese Version of Configuration Schemes for Altera FPGAs) Online 21 Minutes Chinese
Configuration Solutions for Altera FPGAs Online 48 Minutes English
Altera FPGA 配置解决方案 (Chinese Version of Configuration Solutions for Altera FPGAs) Online 55 Minutes Chinese
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Intel FPGA Fundamentals Part 1

Optional Specialized Courses

Notes Course Name Type Duration Language
  Synplify Pro Tips and Tricks Online 43 Minutes English
  Synplify Synthesis Techniques with the Quartus II Software Online 30 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Legacy courses are no longer up to date, but may still contain some useful information. To view the latest courses available, please visit the Course Catalog.

Intel FPGA Fundamentals Part 2

Recommended Courses

These courses assume that you understand the material covered in Fundamentals Part 1 because they cover more advanced topics such as functional simulation, timing analysis, power analysis, debug, and system design using the Qsys tool.

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  Advanced Verilog HDL Design Techniques Instructor-Led / Virtual Class 8 Hours English
  Advanced VHDL Design Techniques Instructor-Led / Virtual Class 8 Hours English
  The Quartus II Software Design Series: Timing Analysis Instructor-Led / Virtual Class 8 Hours English
  Quartus II パーフェクト・コース II : タイミング解析 (Timing Analysis) Instructor-Led Only 8 Hours Japanese
TimeQuest Timing Analyzer: Introduction to Timing Analysis Online 19 Minutes English
TimeQuest Timing Analyzer: TimeQuest GUI Online 37 Minutes English
TimeQuest Timing Analyzer: Quartus Prime Integration & Reporting Online 29 Minutes English
TimeQuest Timing Analyzer: Required SDC Constraints Online 37 Minutes English
TimeQuest时序分析器 (Chinese Version of TimeQuest Timing Analyzer) Online 84 Minutes Chinese
TimeQuestタイミング・アナライザ Online 100 Minutes Japanese
  The Quartus Software Debug Tools Instructor-Led Only 8 Hours English
  The Quartus II Software: Timing, Optimization and Debug (Europe) Instructor-Led Only 16 Hours German
  Quartus IIパーフェクト・コース II :デバッグと解析ツール (Debugging and analysis tools) Instructor-Led Only 8 Hours Japanese
Power Analysis Online 46 Minutes English
Power Optimization Online 48 Minutes English
功耗分析和优化 (Chinese Version: Power Analysis and Optimization) Online 67 Minutes Chinese
SignalTap II Logic Analyzer: Introduction & Getting Started Online 36 Minutes English
SignalTap II Logic Analyzer: Basic Trigger Conditions & Configuration Online 28 Minutes English
SignalTap II Logic Analyzer: Triggering Options, Compilation, & Device Programming Online 28 Minutes English
SignalTap II Logic Analyzer: Data Acquisition & Additional Features Online 30 Minutes English
SignalTap IIロジック・アナライザ Online 87 Minutes Japanese
SignalTap II嵌入式逻辑分析器 (Chinese Version of SignalTap II Embedded Logic Analyzer) Online 54 Minutes Chinese
Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction Online 38 Minutes English
Debugging JTAG Chain Integrity Online 32 Minutes English
Using the Quartus II Software: Chip Planner Online 60 Minutes English
  Introduction to the Qsys System Integration Tool Instructor-Led / Virtual Class 8 Hours English
Introduction to Qsys Online 30 minutes English
Qsys 系统集成工具入门 (Chinese Version of Introduction to Qsys) Online 19 Minutes Chinese
Qsys 基礎編 (Japanese Version of Introduction to Qsys) Online 30 Minutes Japanese
Creating a System Design with Qsys Online 37 Minutes English
使用Qsys创建一个系统 (Chinese Version of Creating a System Design with Qsys) Online 37 Minutes Chinese
Qsysを使用したシステム・デザインの生成方法 (Japanese Version of Creating a System Design with Qsys) Online 40 Minutes Japanese
  System Design with Qsys Pro Online 41 Minutes English
  Design Optimization Using Quartus II Incremental Compilation Instructor-Led / Virtual Class 8 Hours English
  Quartus IIパーフェクト・コース II : デザイン最適化 (Design optimization Using Incremental Compilation) Instructor-Led Only 8 Hours Japanese
Introduction to Incremental Compilation Online 147 Minutes English
渐进式编译入门 (Chinese Version of Introduction to Incremental Compilation) Online 116 Minutes Chinese
Quartus IIインクリメンタル・コンパイル入門 (Japanese Version of Introduction to Incremental Compilation) Online 110 Minutes Japanese
Quartus IIインクリメンタル・コンパイルによるチームベースのデザイン・フロー (Japanese Version of Team-Based Incremental Compilation) Online 70 Minutes Japanese
  Overview of Mentor Graphic's ModelSim® Software Online 1 Hour English
  ModelSim概要 Online 1 Hour Japanese
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Intel FPGA Fundamentals Part 2

Optional Specialized Courses

Notes Course Name Type Duration Language
  Migrating to the Quartus Prime Pro Edition Software Online 34 Minutes English
 

Quartus Prime 開発ソフトウェアへの移行方法 (Japanese Version: Migrating to the Quartus Prime Pro Edition Software)

Online 34 Minutes
Japanese
  Using Spectra-Q Synthesis in the Quartus Prime Software Online 32 Minutes English
 

Quartus Prime 開発ソフトウェアの Spectra-Q エンジンを使用した合成方法 (Japanese Version: Using Spectra-Q Synthesis)

Online 34 Minutes Japanese
  Incremental Optimization with the Quartus Prime Pro Edition Online 26 Minutes English
  SystemVerilog with the Quartus II Software Online 38 Minutes English
  SystemVerilog和Quartus II 软件 (Chinese Version of SystemVerilog with the Quartus II Software) Online 34 Minutes Chinese
  Quartus II によるSystemVerilogのサポート Online 32 Minutes Japanese
  Creating Reusable Design Blocks: Introduction to IP Reuse Online 25 Minutes English
  再利用可能なデザイン・ブロックの生成方法:IP再利用についての概要 (Japanese Ver Creating Reusable Blocks: Introduction to IP Reuse) Online 26 Minutes Japanese
  Creating Reusable Design Blocks: IP Design & Implementation Online 42 Minutes English
  再利用可能なデザイン・ブロックの生成方法:IPデザインとその実装 (Japanese Ver Creating Reusable Blocks: IP Design & Implementation) Online 45 Minutes Japanese
  Creating Reusable Design Blocks: IP Integration with the Quartus II Software Online 25 Minutes English
  再利用可能なデザイン・ブロックの生成方法:Quartus IIソフトウェアを使用したIPの統合 (Japanese Creating Reusable Blocks: IP Integration) Online 25 Minutes
 
Japanese
  Good High-Speed Design Practices Online 36 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Legacy courses are no longer up to date, but may still contain some useful information. To view the latest courses available, please visit the Course Catalog.

Advanced Hardware

Recommended Courses

If you are an experienced hardware engineer and would like to develop advanced FPGA design skills, these are the courses for you. 

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  Advanced Timing Analysis with TimeQuest Instructor-Led / Virtual Class 8 Hours English
Constraining Source Synchronous Interfaces Online 41 Minutes English
约束源同步接口 (Chinese Version of Constraining Source Synchronous Interfaces) Online 39 Minutes Chinese
Constraining Double Data Rate Source Synchronous Interfaces Online 29 Minutes English
约束双倍数据速率源同步接口 (Chinese Version of Constraining Double Data Rate Source Synchronous Interfaces) Online 29 Minutes Chinese
  ダブル・データ・レートのソース同期インタフェースに対する制約 (Japanese Version of Constraining DDR Source Synchronous Interfaces) Online 35 Minutes Japanese
  Advanced Qsys System Integration Tool Methodologies Instructor-Led / Virtual Class 8 Hours English
Advanced System Design Using Qsys: Component & System Simulation Online 28 Minutes English
Advanced System Design Using Qsys: System Verification with System Console Online 25 Minutes English
Advanced System Design Using Qsys: Qsys System Optimization Online 32 Minutes English
Advanced System Design Using Qsys: Utilizing Hierarchy in Qsys Designs Online 22 Minutes English
System Console Online 35 Minutes English
系统控制台 (Chinese Version of System Console) Online 35 Minutes Chinese
Avalon® Verification Suite Online 24 Minutes English
Avalon验证套装 (Chinese Version of Avalon Verification Suite) Online 17 Minutes Chinese
Custom IP Development Using Avalon and AXI™ Interfaces Online 113 Minutes English
Chinese Version: Custom IP Development Using Avalon and AXI Interfaces Online 97 Minutes Chinese
AvalonおよびAXIインタフェースを使用したカスタム・コンポーネント開発 (Japanese Version of Custom IP Development) Online 117 Minutes Japanese
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Advanced Hardware

Optional Specialized Courses

Learn how to close timing on your design. The Stratix® 10 HyperFlex™ classes will teach you advanced performance-boosting techniques that are applicable to any FPGA design. Other courses will teach you to get the most from partial reconfiguration, scripting, and MAX® 10 devices.

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  Timing Closure with the Quartus II Software Instructor-Led / Virtual Class 8 Hours English
Design Evaluation for Timing Closure Online 55 Minutes English
设计评估实现时序逼近 (Chinese Version of Design Evaluation for Timing Closure) Online 41 Minutes Chinese
  Mitigating Single Event Upsets in Arria 10 Devices Online 24 Minutes English
 

Arria 10 デバイスにおける SEU (Single Event Upset) の緩和技法 (Japanese Ver: Mitigating SEU in Arria 10 Devices)

Online 25 Minutes Japanese
  SEU Mitigation in Arria 10 Devices:  Hierarchy Tagging Online 14 Minutes English
  Performance Optimization with Stratix 10 HyperFlex Architecture Instructor-Led / Virtual Class 8 Hours English
  Advanced Optimization with Stratix 10 HyperFlex Architecture Instructor-Led / Virtual Class 8 Hours English
Stratix 10 HyperFlex Architecture Overview Online 25 Minutes English

Stratix10 HyperFlex 架构概述 (Chinese Version of Stratix 10 HyperFlex Architecture Overview)

Online 22 Minutes Chinese

Stratix 10 HyperFlex アーキテクチャの概要 (Japanese Version of Stratix 10 HyperFlex Architecture Overview)

Online 32 Minutes Japanese
Quartus Prime Hyper-Aware Design Flow
 
Online 24 Minutes English

Quartus II超感知设计流程 (Chinese Version of Quartus II Hyper-Aware Design Flow)

Online 25 Minutes Chinese

Quartus II Hyper-Aware デザイン・フロー (Japanese Version of Quartus II Hyper-Aware Design Flow)

Online 38 Minutes Japanese
Using Fast Forward Compile for the HyperFlex Architecture
 
Online 29 Minutes English
为HyperFlex使用快速前向编译 (Chinese Version of Using Fast Forward Compile for the HyperFlex Architecture) Online 24 Minutes Chinese

HyperFlex アーキテクチャにおける Fast Forward Compile ツールの使用 (Japanese Fast Fwd Compile HyperFlex Architecture)

Online 40 Minutes Japanese
Introduction to Hyper-Retiming Online 18 Minutes English
Hyper-Retiming 介绍 (Chinese Version of Introduction to Hyper-Retiming) Online 17 Minutes Chinese
Hyper-Retiming 入門編 (Japanese Version of Introduction to Hyper-Retiming) Online 22 Minutes Japanese
Eliminating Barriers to Hyper-Retiming Online 39 Minutes English

消除Hyper-Retiming中的障碍  (Chinese Version of Eliminating Barriers to Hyper-Retiming)

Online 30 Minutes Chinese
Introduction to Hyper-Pipelining Online 28 Minutes English

Stratix 10 HyperFlex Design: Analyzing Critical Chains

Online 31 Minutes English
Introduction to Hyper-Optimization Online 22 Minutes English
Hyper-Optimization Techniques 1: Loop Analysis and Solutions Online 22 Minutes English
Hyper-Optimization Techniques 2: Pre-Computation Online 9 Minutes English
Hyper-Optimization Techniques 3: Shannon's Decomposition Online 22 Minutes English
Using Design Space Explorer Online 21 Minutes English
デザイン・スペース・エクスプローラ (DSE) の使用 (Japanese Version of Using Design Space Explorer) Online 36 Minutes Japanese
使用Quartus II 顾问和设计空间勘查器实现时序逼近 (Chinese Version of Timing Closure Using Quartus II Advisors) Online 38 Minutes Chinese
Timing Closure Using TimeQuest Custom Reporting Online 24 Minutes English
Best HDL Design Practices for Timing Closure Online 61 Minutes English
时序逼近最佳HDL设计实践 (Chinese Version of Best HDL Design Practices for Timing Closure) Online 51 Minutes Chinese
タイミング収束のためのベストプラクティス (Japanese Version of Best HDL Practices for Timing Closure) Online 51 Minutes Japanese
Using the Quartus II Software: Chip Planner Online 60 Minutes English
  Partial Reconfiguration with Altera FPGAs Instructor-Led Only 8 Hours English
Partial Reconfiguration Online 54 Minutes English
部分重配置 (Chinese Version of Partial Reconfiguration) Online 51 Minutes Chinese
  Using the MAX 10 User Flash Memory Online 26 Minutes English
  Using the MAX 10 User Flash Memory with the Nios II Processor Online 24 Minutes English
  Introduction to Remote System Upgrade in MAX 10 Devices Online 31 Minutes English
  Max10器件远程系统更新(RSU)介绍 (Chinese Version of Introduction to Remote System Upgrade in MAX 10 Devices) Online 25 Minutes Chinese
 

MAX 10 デバイスのリモート・システム・アップグレード機能 (Japanese Introduction to Remote System Upgrade in MAX 10 Devices)

Online 35 Minutes Japanese
  Remote System Upgrade in MAX 10 Devices: Design Flow & Demonstration Online 26 Minutes English
  Max10器件远程系统更新(RSU):设计流程和示例 (Chinese Ver Remote System Upgrade in MAX 10 Devices: Design Flow & Demo) Online 23 Minutes Chinese
  MAX 10 デバイスのリモート・システム・アップグレード機能:デザイン・フロー & デモンストレーション (Japanese Remote System Upgrade: Design Flow) Online 29 Minutes Japanese
  Introduction to Tcl Online 65 Minutes English
  Tcl 脚本语言入门 (Chinese Version of Introduction to Tcl) Online 54 Minutes Chinese
  Quartus II Software Tcl Scripting Online 49 Minutes English
  Quartus II 软件 Tcl 脚本 (Chinese Version of Quartus II Software Tcl Scripting) Online 40 Minutes Chinese
  Quartus II Tclスクリプトの基礎 前編 Online 14 Minutes Japanese
  Command Line Scripting Online 30 Minutes English
  Using the Quartus II Software: Schematic Design Online 5 Minutes English
  Quartus II 软件中的原理图设计 (Chinese Version of Using the Quartus II Software: Schematic Design) Online 6 Minutes Chinese
  Managing Metastability with the Quartus II Software Online 58 Minutes English
  Introduction to Analog to Digital Conversion in MAX 10 Devices Online 20 Minutes English
  Integrating an Analog to Digital Converter in MAX 10 Devices Online 18 Minutes English
  Using the ADC Toolkit in MAX 10 Devices Online 27 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Legacy courses are no longer up to date, but may still contain some useful information. To view the latest courses available, visit the Course Catalog.

I/O Interfaces

Recommended Courses

Reconfigurable devices allow you to use a large number of different, high-speed I/O interfaces. These courses can help you understand the I/O blocks on Intel FPGA devices in order to create your own custom I/O interfaces.

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  Fast & Easy I/O System Design with BluePrint Online 40 Minutes English
 

BluePrint プラットフォーム・デザイナによる迅速で容易な I/O システム・デザイン (Japanese Fast & Easy I/O System Design w/ BluePrint)

Online 41 Minutes
 
Japanese
  I/O Signal Integrity Analysis with Third-Party Tools Online 32 Minutes English
 

サードパーティー製ツールを使用した I/O シグナル・インテグリティの解析方法 (Japanese I/O Signal Integrity Analysis w Third-Party Tools)

Online 41 Minutes Japanese
  SerDes Channel Simulation with IBIS-AMI Models Online 14 Minutes English
  IBIS-AMI モデルを使用したSerDesチャネルのシミュレーション (Japanese Ver: SerDes Channel Simulation with IBIS-AMI Models) Online 17 Minutes Japanese
  高级I/O系统设计 (Chinese Version of Advanced I/O System Design) Online 75 Minutes Chinese
  Transceiver Basics Online 54 Minutes English
  トランシーバー・ベーシック (Japanese Version of Transceiver Basics) Online 44 Minutes Japanese
  收发器基础 (Chinese Version of Transceiver Basics) Online 49 Minutes Chinese
  Building Gigabit Interfaces in 28-nm Devices Instructor-Led Only 8 Hours English
Transceiver Toolkit for 28-nm Devices Online 39 Minutes English
收发器工具包(Chinese Version of Transceiver Toolkit) Online 28 Minutes Chinese
Advanced Signal Conditioning for Stratix IV and Stratix V Receivers Online 19 Minutes English
  Building Interfaces with Arria 10 High-Speed Transceivers Instructor-Led or Virtual Class 8 Hours English
Transceiver Toolkit for Arria 10 Devices Online 26 Minutes English
Generation 10 Transceiver Clocking Online 28 Minutes English
Building a Generation 10 Transceiver PHY Layer Online 37 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

I/O Interfaces

Optional Specialized Courses

Reconfigurable devices allow you to use a large number of different, high-speed I/O interfaces.  These courses help you implement an interface to an external memory device or implement an industry standard communication interface such as Ethernet or PCI Express.

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  高速 I/O インタフェース: アルテラ FPGA を使った、外部メモリとのインタフェース (EMIF) Instructor-Led Only 8 Hours Japanese
Using High Performance Memory Interfaces in Altera 28 nm and 40 nm FPGAs Online 85 Minutes English
使用Altera FPGA中的高性能存储器接口 (Chinese Version: Using High Performance Memory Interfaces in 28 nm & 40 nm FPGAs) Online 100 Minutes Chinese
  Introduction to Memory Interfaces IP in Arria 10 & Stratix 10 Devices Online 41 Minutes English
  第10代器件内存接口IP介绍 (Part 1) (Chinese Ver Introduction to Memory Interfaces IP in Arria 10 Devices) Online 23 Minutes Chinese
  Generation 10デバイスのメモリ・インタフェース 導入編 (Japanese Ver of Intro to Memory Interfaces in Arria 10) Online 37 Minutes Japanese
  Introduction to Hybrid Memory Cubes with Altera FPGAs Online 21 Minutes English
  Integrating Memory Interfaces IP in Arria 10 Devices Online 62 Minutes English
  第10代器件集成的内存接口IP (Part 2) (Chinese Version Integrating Memory Interfaces IP in Arria 10 Devices) Online 41 Minutes Chinese
  Generation 10デバイスにおけるメモリ・インタフェースIPの統合 (Japanese Ver Integrating Memory Interfaces in Arria 10 Devices) Online 49 Minutes Japanese
  Implementing the Hybrid Memory Cube Controller IP in an Altera FPGA Online 32 Minutes English
  Verifying Memory Interfaces IP in Arria 10 Devices Online 27 Minutes English
  第10代器件内存接口IP验证 (Part 3) (Chinese Version Verifying Memory Interfaces IP in Arria 10 Devices) Online 22 Minutes Chinese
  Generation 10デバイスにおけるメモリ・インタフェースIPの検証 (Japanese Ver of Verifying Mem Interfaces in Arria 10 Devices) Online 28 Minutes Japanese
  On-Chip Debugging of Memory Interfaces IP in Arria 10 Devices Online 32 Minutes English
  第10代器件内存接口IP的片内调试 (Part 4) (Chinese Ver On-Chip Debug of Memory Interfaces IP in Arria 10 Devices) Online 16 Minutes Chinese
  Generation 10デバイスにおけるメモリ・インタフェースIPのオンチップ・デバッグ (Japanese Version On-Chip Debug Memory Interfaces Arria 10) Online 22 Minutes Japanese
  Creating PCI Express Links Using FPGAs Instructor-Led Only 8 Hours English
Introduction to the Arria 10 Hard IP for PCI Express Online 31 Minutes English
Customizing the Arria 10 Hard IP for PCI Express Online 31 Minutes English
Connecting to the Arria 10 Hard IP for PCI Express Online 32 Minutes English
Designing with the Arria 10 Hard IP for PCI Express Online 26 Minutes English
Introduction to the 28 nm Hard IP for PCI Express Online 37 Minutes English
Customizing the 28 nm Hard IP for PCI Express Online 35 Minutes English
Connecting to the 28 nm Hard IP for PCI Express Online 30 Minutes English
Designing with the 28 nm Hard IP for PCI Express Online 17 Minutes English
Getting Started with Altera's 40 nm PCI Express Solutions Online 92 Minutes English
アルテラ・トランシーバ搭載デバイスで実現する PCI Express Online 107 Minutes Japanese
  Introduction to the Triple-Speed Ethernet MegaCore® Function Online 28 Minutes English
  Implementing the Triple-Speed Ethernet MegaCore Function Online 24 Minutes English
  Altera 10/100/1000 Mb以太网解决方案简介 (Chinese Version of Intro to10/100/1000 Mb Ethernet) Online 66 Minutes Chinese
  Introduction to the 10Gb Ethernet PHY IP Cores Online 28 Minutes English
  Introduction to the Low Latency 10Gb Ethernet MAC IP Core Online 30 Minutes English
  Using the 10Gb Ethernet Design Examples Online 19 Minutes English
 

JESD204B MegaCore IP Overview

Online 27 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Legacy courses are no longer up to date, but may still contain some useful information. To view the latest courses available, visit the Course Catalog.

DSP

Recommended Courses

Do you have a digital signal processing (DSP) design that you would like to implement in an Intel FPGA? These courses will teach you how to use the tools that can help create that design faster and more efficiently.

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

DSP

Optional Specialized Courses

Notes Course Name Type Duration Language
Building Video Systems Online 25 Minutes English
使用Altera视频工作台构建视频系统 (Chinese Version of Building Video Systems) Online 77 Minutes Chinese
  Introduction to Graphics Online 12 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Legacy courses are no longer up to date, but may still contain some useful information. To view the latest courses available, visit the Course Catalog.

Embedded Hardware

Recommended Courses

These courses will teach you how to create FPGA hardware designs using the Nios II or ARM processors that are available on Intel FPGA devices. 

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led / virtual courses.

Notes Course Name Type Duration Language
  Designing with the Nios II Processor Instructor-Led Only 8 Hours English
  組込みシステム: Nios II & Qsys 基礎編 (Embedded Systems: Nios II & Qsys Fundamentals) Instructor-Led Only 8 Hours Japanese
Using the Nios II Processor: Hardware Development Online 27 Minutes English
Using the Nios II Processor: Software Development Online 10 Minutes English
Using the Nios II Processor: Custom Components and Instructions Online 11 Minutes English
使用Nios II 处理器 (Chinese Version of Using the Nios II Processor) Online 64 Minutes Chinese
Nios II & Qsys(システム統合ツール) 基礎編 (Nios II & Qsys (system integration tool) Fundamentals) Online 8 Hours Japanese
  Designing with an ARM-based SoC Instructor-Led / Virtual Class 8 Hours English
  ARMベース SoCハードウエア開発 (SoC Hardware) Instructor-Led Only 8 Hours Japanese
Hardware Design Flow for an ARM-based SoC Online 40 Minutes English
基于ARM的芯片系统硬件设计流程(Chinese Version: Hardware Design Flow for an ARM-based SoC) Online 47 Minutes Chinese
ARMベースSoC向けハードウェア・デザイン・フロー (Japanese Version: Hardware Design Flow for an ARM-based SoC) Online 53 Minutes Japanese
SoC ハードウエア概要 パート1(Japanese Version of SoC Hardware Overview Part 1) Online 68 Minutes Japanese
SoC ハードウェア概要 パート2 (Japanese Version of SoC Hardware Overview Part 2) Online 44 Minutes Japanese

SoC Hardware Overview: the Microprocessor Unit

Online 34 Minutes English
SoC 硬件概述: 微处理器单元 (Chinese Version of SoC Hardware Overview: the Microprocessor Unit ) Online 35 Minutes
 
Chinese

SoC Hardware Overview: Interconnect and Memory

Online 33 Minutes English

SoC 硬件综述: 互连和存储  (Chinese Version of SoC Hardware Overview: Interconnect and Memory)

Online 27 Minutes Chinese
SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals Online 26 Minutes English

SoC 硬件综述:系统管理,调试,及通用外围设备 (Chinese Ver of SoC Hardware Overview: System Mngmt, Debug, GP Peripherals)

Online 28 Minutes
 
Chinese
SoC Hardware Overview: Flash Controllers and Interface Protocols Online 20 Minutes English
SoC 硬件概述: Flash 控制器和接口协议 (Chinese SoC Hardware Overview: Flash Controllers and Interface Protocols) Online 20 Minutes Chinese
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Legacy courses are no longer up to date, but may still contain some useful information. To view the latest courses available, visit the Course Catalog.

Software Development

Recommended Courses

Are you a software developer who is targeting Intel FPGA devices?  Learn how to use the necessary tools to program and debug Nios® II and ARM® processors on Intel FPGA devices.

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  Developing Software for the Nios II Processor Instructor-Led Only 8 Hours English
Nios II Software Tools and Design Flow Online 22 Minutes English

Nios II ソフトウェアに搭載されたツールとそのデザイン・フロー (Japanese Version of Nios II Software Tools and Design Flow)

Online 28 Minutes Japanese
Nios II 处理器开发软件:工具简介 (Chinese Version of Nios II Processor: Tools Overview) Online 24 Minutes Chinese
Nios II プロセッサソフトウェア開発: デザイン・ツール概要 (Nios II processor software development: design tools Overview) Online 31 Minutes Japanese
Nios II 处理器开发软件:设计流程(Chinese Version of Nios II Processor: Design Flow) Online 24 Minutes Chinese
Developing Software for the Nios II Processor: Nios II Software Build Tools for Eclipse Online 14 Minutes English
Nios II Software Build Tools for Eclipse and BSP Editor (Quartus® II Software 10.0 Update) Online 26 Minutes English
Nios II Software Tools for Eclipse:導入編 Online 17 Minutes Japanese
Developing Software for the Nios II Processor: HAL Primer Online 20 Minutes English
Nios II 处理器开发软件:HAL入门 (Chinese Version of Nios II Processor: HAL Primer) Online 16 Minutes Chinese
Nios II プロセッサソフトウェア開発: HAL Online 14 Minutes Japanese
  Lauterbach Debug Tools Online 16 Minutes English
  Designing and Developing Software for an ARM-based SoC (two-day course) (Europe) Instructor-Led Only 16 Hours German
  Developing Software for an ARM-based SoC Instructor-Led / Virtual Class 8 Hours English
  ARM ベース SoC ソフトウエア開発 Instructor-Led Only 8 Hours Japanese
Software Design Flow for an ARM-based SoC Online 27 Minutes English
基于ARM的SoC的软件设计流程(Chinese Version: Software Design Flow for an ARM-based SoC) Online 33 Minutes Chinese
ベース SoC 向けソフトウェア・デザイン・フロー (Japanese Verion of Software Design Flow for ARM-based SoC) Online 40 Minutes Japanese

Creating Second Stage Bootloader for Altera SoCs

Online 31 Minutes English
Getting Started with Linux for Altera SoCs Online 34 Minutes English
アルテラ SoC 向け Linux の概要 (Japanese Version of Getting Started with Linux for Altera SoCs) Online 57 Minutes Japanese
SoC Bare-metal Programming and Hardware Libraries Online 28 Minutes English
  Secure Boot with Arria 10 SoC FPGAs Online 17 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Software Development

Optional Specialized Courses

Are you a software developer who is targeting Intel FPGA devices? Learn how to optimally use the OpenCL™ language to accelerate your algorithm using a heterogeneous processing platform. 

The following table shows the recommended order of courses to take. Online courses are listed below any related instructor-led or virtual courses.

Notes Course Name Type Duration Language
  Introduction to OpenCL for Altera FPGAs Instructor-Led / Virtual Class 8 Hours English
Introduction to Parallel Computing with OpenCL on FPGAs Online 21 Minutes English
在FPGA上使用OpenCL实现的并行计算 (Chinese Version: Introduction to Parallel Computing with OpenCL on FPGAs) Online 23 Minutes Chinese
OpenCL による並列コンピューティング:入門編  (Japanese Version of Introduction to Parallel Computing with OpenCL) Online 33 Minutes Japanese
Writing OpenCL Programs for Altera FPGAs Online 52 Minutes English
编写OpenCL程序 (Chinese Version: Writing OpenCL Programs for Altera FPGAs) Online 46 Minutes Chinese
アルテラ FPGA 向け OpenCL プログラム記述方法 (Japanese Version: Writing OpenCL Programs for Altera FPGAs) Online 55 Minutes Japanese
Running OpenCL on Altera FPGAs Online 25 Minutes English
在Altera FPGA 中运行OpenCL程序(Chinese Version: Running OpenCL on Altera FPGAs) Online 22 Minutes Chinese
アルテラ FPGA 向け OpenCL実行方法(Japanese Version: Running OpenCL on Altera FPGAs) Online 29 Minutes Japanese
  Optimizing OpenCL for Altera FPGAs (2 Day Course) Instructor-Led / Virtual Class 16 Hours English
OpenCL: Single-threaded vs. Multi-threaded Kernels Online 17 Minutes English
OpenCL:单线程vs多线程内核  (Chinese Version: OpenCL: Single-threaded vs. Multi-threaded Kernels) Online 12 Minutes Chinese
OpenCL:シングルスレッド・カーネル vs マルチスレッド・カーネル (Japanese OpenCL: Single-Threaded vs. Multi-Threaded Kernels) Online 19 Minutes Japanese
 

Developing a Custom OpenCL BSP

Instructor-Led / Virtual Class 8 Hours English
Building Custom Platforms for Altera SDK for OpenCL Online 57 Minutes English
创建Altera SDK for OpenCL定制平台 (Chinese Version: Building Custom Platforms for Altera SDK for OpenCL) Online 41 Minutes Chinese

アルテラ SDK for OpenCL のカスタム・プラットフォームの構築 (Japanese Building Custom Platforms for Altera SDK for OpenCL)

Online 80 Minutes Japanese
  OpenCL Optimization Techniques: Image Processing Algorithm Example Online 8 Minutes English
  OpenCL Optimization Techniques: Secure Hash Algorithm Example Online 7 Minutes English
Notes:

[1]  This course has a subset of material compared to the instructor-led course above

[2]  This course has more detail on a particular topic compared to the instructor-led course

Legacy courses are no longer up to date, but may still contain some useful information. To view the latest courses available, please visit the Course Catalog.