Date: January 28 January 31, 2014
Altera® Featured Technology: Stratix® V FPGAs, Transceiver Technology, DSP Solutions, Signal Integrity
Santa Clara Convention Center
Region: North America Events
Event URL:

Presents a Variety of Papers and Tutorials at DesignCon 2014

At DesignCon 2014, Altera will showcase how its FPGA architectural innovations and state-of-the-art technologies enable high-speed I/O performance and power efficiency, best-in-class signal and power integrity, and digital signal processing capabilities. IEEE Fellow Dr. Mike Peng Li, Altera research and development architect and engineer, kicks off the company’s participation at the show with a half-day jitter and signal integrity tutorial on January 28. In addition, Altera will present nine technical papers while also lending expertise to two panel discussions.

Hear From Jitter and SERDES Architecture Expert and IEEE Fellow, Dr. Mike Peng Li:

Date/Time Tutorial Topic Topic
Thursday, January 30
9:00 a.m. – 12:00 p.m.
Ballroom F
Design and Verification for High-Speed I/Os at Multiple to 56 Gbps with Jitter, Signal Integrity, and Power OptimizationThis session reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process technology advancements for high-speed links, with an emphasis on jitter and signal integrity for up to 10 to 56 Gbps high-speed I/Os. Example studies on design and validation methods will be presented, as well as the practical issues of design tradeoff, multiple I/O standards support, jitter reduction, signal integrity mitigation, power optimization, jitter/signaling interactions with equalizations and clock recovery, and advanced verifications.
Tuesday, January 28
4:45 p.m. – 6:00 p.m.
Panel Discussion
Ballroom E/F
Battle on the Chip: Embed vs. De-Embed?

As SERDES speeds increase beyond 25G, practical characterization methods like "put a scope on it" leave much to be desired. There are test specifications being drafted which emphasize the need to de-embed measurement channels to get more accurate characterization results; and some signal integrity practices advocate the embedding of connector/backplane effects to get a more realistic view of system performance. Test and measurement vendors have techniques for both in their instruments; but in practice, which one, or both, does the signal integrity engineer embrace?

Panel Discussions

Date/Time Tutorial Topic Topic
Tuesday, January 28
9:00 a.m. – 12:00 p.m.
Ballroom E
High-Density, High-Performance Package and 2.5-D/3-D Interconnect Design

This session is targeted at design and technology enablement for high-density and high-performance heterogeneous multi-chip integration with 2.5-D and 3-D interconnects. The multi-chip integration is defined by a broad range of high density interconnect technologies including high density PoP type package, SiP, SoP, TSV, and interposer. It differentiates from traditional MCP, POP, and coarse TSV silicon interposer in that the proposed track address interconnect density at silicon level targeting at 100G/400G and 1TB wireline, wireless, military, and high performance computing markets. Enormous market opportunity has attracted investment into research institutes, fabless, IDMs, foundries, and OSATs. The engineering development in the design and process has become significant portion of the semiconductor industry and contending the traditional monolithic IC and packaging. This session will bring unique nature and many interests facing this growing industry sector.

Speaker: John Xie

Wednesday, January 29
9:20 a.m. – 10:00 a.m.
Ballroom K
Lessons Learned: How to Make Predictable PCB Interconnects for Data Rates of 50 Gbps and Beyond

Design of PCB interconnects for data channels running at bitrate 50 Gbps is a very challenging problem that requires analysis and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This session shares our experience in building a practical methodology to make predictable 50 Gbps interconnects. Substantial part of interconnects can be simulated with transmission line models that require identification of causal broadband dielectric and conductor roughness models. It is shown that separation of losses between the roughness and dielectric models is an essential element of such identification. Examples of proper and improper material models identification and consequences are provided in the session. Accurate prediction of interconnect behavior also requires localization and 3D EM analysis for all transitions or discontinuities. Examples of optimized interconnects designed for 50 Gbps channels and validated measurements are also provided.

Speaker: Jihong Ren

3:45 p.m. – 5 p.m.
Ballroom F
Post-Equalization Metrics at 25 Gbps and Beyond

Technical leaders will discuss techniques and methods for measuring the eye at the output of the receiving equalizer. How accurate are these metrics? How strongly do they correlate with BER statistics? The panel will discuss the impact on link performance of channel loss, discontinuities, crosstalk, and power supply noise. How do these familiar physical effects show up in post-equalization eye metrics? Are the metrics valid for verifying technology choices and long-term reliability? How can signal integrity analysis tools help to ensure a more robust SerDes design?

Jihong Ren

Technical Papers Presented by Altera

Date/Time Tutorial Topic Topic
Wednesday, January 29
8:30 a.m. - 9:10 A.M.
Ballroom C/D
10.3 Gbps Link Optimization and Its Impact on Jitter

This session presents a case study of signal integrity optimization of a SFF8431 10.3 Gbps link and its impact on Inter-Symbol Interference (ISI) portion of the total jitter. Optimization is done both using TDR simulations and s-parameter simulations. The impact of reflection and insertion loss on ISI is quantified by simulation and measurements. In addition, effectiveness of pre-emphasis in reducing ISI on a high-reflection channel and low-reflection channel is also quantified.

Paper Authors: Aman Aflaki, Janani Chandrasekhar, Bipin Dhavale, John Jones, Timothy Lu, Alexander Razmadze. Shishuang Sun

11:05 a.m. – 11:45 a.m.
Ballroom H
Optimizing DDR4 PHY Design to Reduce the System-Level Jitter Impact by Supply Noise

As DDR I/O speed continues to increase, uncorrelated timing jitter becomes a significant portion of channel timing budget. The dominant component of uncorrelated timing jitter comes from power supply noise induced jitter (PSIJ). DDR system uses a clock forwarding architecture using a strobe signal which tracts a large portion of PSIJ in data signal. Due to inherent 90 degree offset between data and strobe signals, a significant amount of high-frequency jitter is not tracked. To avoid, system overdesign or failure, it is critical to investigate the net timing margin loss due to supply noise. Using comprehensive jitter analysis including all the key critical timing circuitry and power distribution network including on-chip regular, the overall system performance can be optimized with a proper balance of design cost and performance. In this work, we consider DDR PHY design to illustrate our system-level modeling approach to on-chip circuitry and PDN co-design.

Paper Authors: Dan Oh, Yujeong Shim

2:50 p.m. - 3:30 p.m.
Ballroom E
Analyzing Impact of On-Chip Supply Noise Induced Jitter

In this session, the new framework for power integrity analysis for core logic blocks is presented. Balancing on-chip timing budget becomes more challenging as both data and clock jitter increase due to large power noise. Conventional power integrity (PI) analysis focuses on reducing supply noise and does not provide timing jitter information. This session proposes a general framework to model timing jitter due to supply noise. The proposed methodology can be used to define power distribution network (PDN) design requirements. This timing jitter-based PDN design leads to significant reduction in the pessimism associated with either conventional target impedance concept, or static or dynamic power integrity analysis. The formulation covers both a single-power domain and multi-power domain cases. The frequency domain formulation is further approximated to derive a flow which can be implemented in conventional static timing analysis (STA) flow.

Paper Authors: Karthik Chandrasekar, Guang Chen, Wern Shin Choo, Dan Oh , Alexander Razmadze , Yujeong Shim, Shishuang Sun

Thursday, January 30
8:30 a.m. - 9:10 a.m.
Ballroom H

High-Speed Link Simulation Strategy for Meeting Ultra Long Data Pattern Under Low BER Requirements

Link simulation has become an essential step in developing successful and cost-efficient high-speed serial links. Today's high-speed serial links typically consist of a transmitter/receiver pairing with equalization mechanisms and numerous channel components. The aforementioned physical factors then interact with the link's operational conditions like data patterns and BER requirements while noises and jitter, from the devices and channels, need to be properly simulated and budgeted. The enormous test space usually exceeds the practical limits of computation capabilities. We developed a practical simulation strategy in determining the simulation methodology and configurations which will facilitate an accurate and effective link stress test platform. The theoretical foundation, mathematical model, simulations, lab measurement results, and practical applications will be presented.

Paper Authors: Mike Peng Li, Masashi Shimanouchi, Hsinhu Wu

2:50 p.m.- 3:30 p.m.
Ballroom K
RX Jitter, Jitter Measurement, and Relation to Jitter Tolerance and Overall Link PerformanceJitter has been used to evaluate each link component's performance and to relate it to the overall link performance. Although a lot of studies have been made on TX jitter, its measurement methods, lossy channel characteristic, and equalization techniques by TX and RX, there has not been much discussion on RX jitter. We will discuss an RX jitter model, which is considered as the break down into the jitter components, and is closely related to the measurement method. Second, we will discuss how to measure RX jitter. Third, we will discuss how RX jitter is related to jitter tolerance to complete the story.

Paper Authors: Mike Peng Li, Masashi Shimanouchi, Hsinhu Wu
Friday, January 31
9:10 a.m. – 10:30 a.m.
Ballroom F
A Novel Scheme to Improve Power Distribution Networks for 20nm FPGA Designs and BeyondPower supply noise induced jitter (PSIJ) is one of the critical bottlenecks for I/O signal performance. Good power distribution network (PDN) is a must for high-end system designs. Due to design limitation in die and package, providing sufficient on-die capacitor (ODC) or on-package capacitor (OPD) is a very challenging task. This session presents a novel on-die decoupling scheme which places decoupling caps in core area and connects to I/O area by package interconnects. The presented method is applied to DDR interface in med-end FPGA devices. Excellent SSN improvement is achieved by implementing this scheme.

Paper Authors: Kundan Chand, Hui Liu
Dan Oh