Intel + Altera = Efficient HPC Coprocessing

Intel + Altera = Efficient HPC Processing Net Seminar

Available Now, On-Demand!
Featured Technology: Stratix® III FPGAs
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Overview

If you’re ready to accelerate your processor-intensive applications to the next level of performance and efficiency, you need to view this net seminar. Using the Front-Side Bus (FSB), Altera’s FPGAs communicate with Intel® processors to accelerate algorithms and applications up to 100x. In this 30-minute net seminar, you’ll see how you can take advantage of these new efficiencies to raise the bar on your HPC application’s performance.

Join Altera’s Senior Vice President of R&D and Intel's Marketing Manager of Accelerated Computing to learn:

  • How FPGAs coprocessors improve the price/performance ratio for application acceleration
  • Why Intel’s FSB is an ideal coprocessor interface
  • How writing applications in C and going directly to hardware makes your development process more efficient

Who Should View

  • Financial, medical, and insurance industry IT managers
  • Engineering and technical managers
  • System architects

Presenters

Misha Burich
Misha Burich
Senior Vice President, Research and Development, Altera

Dr. Burich joined Altera’s in December 2000 as senior vice president of software engineering and in 2004 he also assumed the responsibility for system engineering. He currently manages R&D for all new FPGA architectures, software products, embedded processors, intellectual property libraries, and system solutions. Prior to joining Altera, he served as a vice president of R&D at various EDA companies, including Cadence Design Systems, Mentor Graphics, Silicon Compiler Systems, and Silicon Design Labs, which he co-founded in 1984. Dr. Burich began his career at Bell Laboratories in 1978.

Avinash (Nash) Palaniswamy
Avinash (Nash) Palaniswamy
Marketing Manager, Accelerated Computing, Server Product Group, Intel® Corporation

Dr. Nash has been at Intel since October 2005, and currently manages the Accelerated Computing marketing efforts in the Server Product Group. His responsibilities include the strategy and marketing efforts around Intel® QuickAssist Technology enabled FSB-FPGA Accelerators, and other accelerator related technologies such as SOA/XML, etc. His prior responsibilities at Intel included being the World Wide Web Consortium Advisory Committee representative from Intel. Prior to joining Intel as part of the acquisition of Conformative Systems, an XML Accelerator Company, he has served in several senior executive positions in the industry including being the Director of System Architecture at Conformative Systems, CTO/VP of Engineering at MSU Devices, and Director of Java Program Office and Wireless Software Strategy in the Digital Experience Group of Motorola, Inc. Dr. Palaniswamy holds a B.S. in Electronics and Communications Engineering from Anna University (Chennai, India) and an M.S. and Ph.D. from the University of Cincinnati in Electrical and Computer Engineering.

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