Though high-speed serial links increase data throughput and reduce the number of traces on a board, a different set of challenges arise when designing these systems. This seminar provides useful guidelines and techniques when designing a high-speed channel. The seminar will cover a channel model case study that includes how to address the challenges of designing at high data rates (BGA breakout, crosstalk, vias, DC block capacitor, and an SMA connector). These challenges are tied in and are implemented in a complete end-to-end channel simulation.
At this net seminar, you'll learn how to:
- Address high-speed channel design challenges
- Analyze modeled and simulated high-speed interconnects
- Employ a simulation environment for an end-to-end channel
Who Should View
- System architects
- Hardware and system design engineers
- FPGA developers
- Signal integrity engineers
All participants who attend this net seminar between June 11, 2007 and July 27, 2007 and complete the post-presentation survey will be entered into the drawing for a chance to win an RCA Lyra 20GB Audio/Video Jukebox (US$160 value)!
High-Speed Design Engineer, Component Applications
Leonard Dieguez joined Altera in September 2005 as a high-speed design engineer working in the component applications’ high-speed board development group. Mr. Dieguez has over 15 years of industry experience, including eight years in serial communications. He began his career in serial communications at JNI designing Fibre Channel host bus adapters (HBAs). He published papers on novel CDR techniques using sampled delay lines in FPGA fabrics. Mr. Dieguez graduated with his BSEE from the University of South Florida in 1986, with major course work in microwave theory and distributed networks. After graduation, Leonard Dieguez served in the United States Navy as a helicopter pilot and is a veteran of the Gulf war.
Sr. Technical Marketing Engineer
As a senior technical marketing engineer for Altera’s high-end FPGA product lines, Salman Jiva is responsible for the technical marketing and analysis of the signal integrity and high-speed interfaces for Altera® FPGAs. Prior to joining Altera, he spent six years at Cisco Systems as an ASIC signal integrity engineer for their enterprise line of switches. Mr. Jiva holds an MS in Electrical Engineering from Santa Clara University with a concentration in communication systems.
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