Partitioning FPGA Designs for Redundancy and Information Security

Available Now, On-Demand
Length:
20 minutes

Ensure high up-time and reliability for designs requiring fault tolerance, redundancy, and/or information security. This webcast uses motor control and software-defined radio (SDR) application examples to show how you can use FPGAs to partition and separate critical design elements.



View the webcast to:

  • View a demo on using software to implement design separation on an FPGA
  • Learn how you can design fault-tolerant logic using new software-instantiated design separation tools
  • See how Altera's new low power, secure Cyclone® III LS FPGAs provide separation for complete functional independence on a single chip

Presenter:

Tom Schulte

Tom Schulte
, Sr. Marketing Manager

View Free Webcast