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Intel® How-To Videos

The Engineer-to-Engineer (E2E) video playlist are how-to videos to help you get your FPGA and SoC FPGA projects up and running. The videos are made by Intel’s engineers for FPGA designers.

Title	Description
Constrain the IOPLL Location for LVDS SERDES in Arria 10	Watch this video to learn how to properly constrain the IOPLL location for a LVDS SERDES in the Arria 10 device.
How to perform link test with Arria 10 LVDS SERDES in DPA FIFO mode	This video shows users how to configure the LVDS SERDES TX instance and RX instance in DPA FIFO mode. The video also demonstrates a link test using the Arria 10 GX FPGA Development Kit.
Generating PHYLite example design simulation in ModelSim in 16.1 with Arria10	This tutorial video demonstrates how to generate simulation files from custom PHYLite settings in Qsys. Additionally, learn how to set up the simulation environment in ModelSim to run PHYLite simulations.
Arria 10 SoC External U-Boot Configuration for the Golden System Reference Design	Watch this video to learn about Arria 10 SoC external U-boot configuration. Booting is executed directly from FPGA memory such as the FPGA On-chip RAM, as opposed to the SoC RAM.
Understanding and Utilizing the USB Blaster Interface to Configure Intel FPGAs	This video describes how to use and debug the USB Blaster interface to configure Intel FPGAs.
How to Configure Arria 10 / Stratix 10 Altera PHYLite Input and Output Delay Constraints	Watch this video to learn how to configure Arria 10 and Stratix 10 PHYLite input and output delay constraints.
Booting up Stratix 10 UEFI with SOCVP and perform TFTP with the host machine	In this video, the user will learn how to boot up Stratix 10 UEFI with SoCVP and how to setup TFTP server in a Linux machine and perform TFTP test when booting with the DXE console
Nios II booting methods	This video discusses different methods of booting the Nios II soft processor.
Using a Generic Component as a Blackbox in Qsys Pro	Watch this video to learn how to use the generic component implementation, blackbox. The generic component is a special type of IP component introduced in Qsys Pro that enables isolated IP instantiation or blackboxing.
Package deskew in Intel FPGA External Memory Interfaces	This video will explain how to setup package de-skew in all External Memory Interface protocols and how package de-skew can help to improve timing closure.
Stratix V SDI Link Test Training Simulation	This video demonstrates how to run the Stratix V SDI IP core link test training and simulation.
How to Estimate Arria 10 /Stratix 10 PHYLite Input and Output Path Latency	This video demonstrates how to estimate the latency of input and output paths in Arria 10/Stratix 10 Intel FPGA PHYLite context through simulation.
How to Configure Arria 10 PhyLite Timing Constraints	How to configure Arria 10 PHYLite input and output delay constraints using the PHYLite IP GUI.
How to Build and Test a RLDRAM3 Design for Arria 10 Using the EMIF toolkit	This video shows the user how to build an RLDRAM3 design using the Arria 10 development kit . Additionally, it uses the EMIF toolkit to check the calibration status of the RLDRAM3 design.
Ethernet ping test using Telnet from PC to the MAX 10 Development Kit	This video demonstrates using the MAX10 FPGA Development Kit running a Triple-Speed Ethernet design to verify the PHY Auto-Negotiation process, check the network connectivity and speed, and performing Ping test using Telnet from PC to toggle the LEDs on the Development Kit.
Enable Reverse Serial Pre-CDR Loopback in Stratix V GT Native PHY IP Using Dynamic Reconfiguration	This video shows users how to enable the reverse serial pre-CDR loopback mode in the Stratix V GT transceivers using dynamic reconfiguration. Additionally, learn to perform a link test in Modelsim simulation.
Simulating Arria 10 RLDRAM3 Using the Vendor Memory Model	This video shows users how to run an example design simulation by to replacing Intel PSG's generic memory model with the vendor memory model.
Switching the CDR Reference Clock Source on Arria 10 FPGAs	This video shows users how to use dynamic reconfiguration to switch the CDR refclks with the embedded streamer and multiple reconfiguration profiles in an Arria 10 device.
Reading the DFE tap values in Arria10 Native PHY	This video shows the user how to read the converged DFE tap values in the Arria 10 Native PHY using system console.
How to Generate Arria 10 EMIF Example Design	This video demonstrates how to generate an Altera Arria 10 FPGA EMIF (external memory interface) example design using the Quartus software.
Intel FPGA EMIF Device Selector	This is a tutorial and introduction of the External Memory Interface Device Selector. The tutorial will show you the Device Selector GUI and a walkthrough of the Bandwidth Tool.
Intel FPGA EMIF (External Memory Interfaces) Resources and Pin Planning Tool	Watch this video to learn about the Resources and Pin Planning Tool. The tool is used to estimate FPGA EMIF design resource utilization (IO, clocks, DLL, PLL) and perform pin planning without the need to create a design.
old Arria 10 を用いたプリ・エンファシスの基本 (Arria 10 Transceivers: Pre-Emphasis Basics)	高速信号における信号品質(Signal Integrity)補償である、プリ・エンファシスについて説明し、Arria 10 を用いてシミュレーション、実機波形を比較しプリ・エンファシスの実動作を理解する Learn the basics of the Arria 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements
How to build the Minimal Preloader (MPL)	This video demonstrates how to build Altera minimal preloader (MPL) software and use it to load application software on a development kit with an Altera SoC.
How to simulate Cyclone V 8b10b IP byte ordering	This video shows the user how to perform manual word alignment and byte ordering in the Cyclone V Native PHY with 8b10b and double-width PCS mode.
How to Design, Configure, and Execute a Basic Video Streaming Qsys System	This video explains the design, configuration and execution of a video stream Qsys system. Additionally, it provides details on the IP used in the project, followed by a demo.
Write and Run Bare Metal C Programs for ARM DS-5 AE for Altera SoCs	Watch this video to learn about running bare metal c programs on the ARM HPS. Additionally see a demonstration of the Hello World template project.
Write a C/C++ application for Altera Cyclone V SoC Dev Kit using ARM DS-5 AE	Watch this video to lean how to write a C/C++ application that will run on the Intel Cyclone V SoC Dev Kit using ARM DS-5 AE.
Using the Soft NIOS Processor to Debug Arria 10 External Memory Interfaces	This video describes using the Soft NIOS Processor for On-Chip Debugging. The video also provides explanation of the feature and an example usage case.
How to port HWLIB code over to UEFI code Part 2	Watch this video to learn how to port HWLIB code over to UEFI code.
Scalable 10G MAC + 1G/10G PHY with 1588 Design Example Hardware Demo	This scalable design serves as a good example and reference to show Altera 10G Ethernet MAC IP and 1G/10G PHY IP with IEEE 1588 feature. Learn how to perform the design hardware test and also how to modify the hardware tcl script to specify test purpose.
Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 2)	The Quartus II RTL Viewer, State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.
Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 1)	The Quartus II RTL Viewer, State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.
Power Supply, Ripple & Load Transient Terms and Correct Way to Measure Ripple	This video discusses how power supply ripple and load transients play into the tight requirements of the Vcore on FPGAs and other large chips. Additionally, a discussion on the appropriate way to measure ripple is also included.
PCIe Avalon Memory Master DMA reference design in Arria 10	In this 2 part video, the user will learn how to setup the hardware and run the PCIe AVMM DMA reference design in Arria 10 devices for both the Linux and Windows Operating System.
Optimizing Quartus II with Design Explorer (DSE)	This video shows how to optimize Quartus II with Design Space Explorer.
MAX 10 booting NIOS Processor - Part 2	This video demonstrates how to boot an Altera Nios II processor from a MAX 10 FPGA with different configuration methods. This Part 2 video shows how the boot copier copies Nios II application from Intel FPGA on-chip Flash to OCR/External RAM.
MAX 10 booting NIOS Processor - Part 1	This video demonstrates booting a Nios II processor from a MAX 10 FPGA with different configuration methods. This Part 1 video shows how to boot a Nios II processor from Intel FPGA On Chip RAM.
MAX 10 External Memory Interface Implementation and Debug - Part 2	This 2 part video provides an overview of MAX 10 External Memory Interface (EMIF) features, and UniPHY IP implementation and debug.
MAX 10 External Memory Interface Implementation and Debug - Part 1	This 2 part video provides an overview of MAX 10 External Memory Interface (EMIF) features, and UniPHY IP implementation and debug.
Manage device IO with Pin Planner	Learn about managing device IO using the pin planner tool in Quartus.
How to design debug and execute a basic Multi-core Nios system.	This video shows how to create an Altera multi-Nios processor design and showcases the importance of protecting shared peripherals in a multi-core system.
Introduction to the JNEye link analysis tool.	Learn how the Intel FPGA JNEye tool provides a highly-optimized tool flow for link analysis.
Address Span Extender Qsys Component	The Address Span Extender creates a windowed bridge and allows memory-mapped master interfaces to access a larger or smaller address map than the width of their address signals allow. This video explains the Address Span Extender Qsys component.
Getting Started With the TimeQuest Timing Analyzer	Learn the basics of setting up and generating timing reports with the TimeQuest Timing Analyzer within the Altera Quartus II software.
Getting started with the Quartus New Project Wizard	Watch this video to learn about the New Project Wizard in the Quartus II Software.
JTAG External Tracing on Intel FPGA SoCs Using Lauterbach	This video gives a brief introduction to the Intel FPGA SoC board and Lauterbach tracing. Additionally a Step-by-step demonstration on how to debug and trace bare-metal program with Lauterbach is included.
Running the preloader with the ARM DS-5 debugger	Learn to use the ARM DS-5 Debugger with the Preloader on the Intel FPGA Cyclone V SoC Development Kit.
Debug techniques for Ethernet / Nios designs - part 2	Watch this video to learn debug techniques for Ethernet / Nios designs.
Debug techniques for Ethernet / Nios designs - part 1	Watch this video to learn debug techniques for Ethernet / Nios designs.
Enpirion power products voltage mode versus current mode	Watch this video to learn about voltage mode versus current mode in Enpirion power products.
Configuring the sampling rate for dual ADC toolkit in MAX 10	This video introduces the Max 10 ADC IP configurable sampling rate feature, logic simulation and dual ADC toolkit.
How to Use the Altera Board Skew Parameter Tool	This video demonstrates how to use the Board Skew Parameter Tool to assist in calculating board skew parameters needed when generating an Intel FPGA external memory interface IP
Arria 10 Configuration of a Simplex Transceiver	This video explains how to place a Arria 10 simplex transceiver with dynamic reconfiguration in the same physical transceiver channel.
Arria 10 triple rate SDI II IP Hardware implementation and verification	This video demonstrates the triple rate SDI II IP reference design in Arria 10 development kits.
Preserve Compilation Results for Migration to Newer Quartus II Releases	Watch this video to learn about Quartuses backwards compatible feature which preserves compilation results.
Automated PowerPlay Early Power Estimator parameter generation utilizing Quartus Software.	Watch this video to learn how Quartus software could be used to generate the .csv file for power estimation. Additionally, learn to import the files generated to the PowerPlay Early Power Estimation tool.
How to Customize UEFI Bootloader	Watch this video to learn how to customize the UEFI bootloader.
How to use the UEFI Pit-Stop Utility - Part 1	The UEFI Pit-Stop utility is a console in the PEI phase of UEFI. This video teaches users how to access memory IO and memory peripherals such as Nand, Qspi, and Sdmmc using provided PitStop commands.
How to use the UEFI Pit-Stop Utility - Part 2	The UEFI Pit-Stop utility is a console in the PEI phase of UEFI. This video teaches users how to access memory IO and memory peripherals such as Nand, Qspi, and Sdmmc using provided PitStop commands.
How to Port HWLIB Code Over to UEFI Code Part 1	Watch this video to learn how to port HWLIB code over to UEFI code.
Arria 10: Using A Single MIF File to Store Multiple PLL Configuration	This video is an introduction to Arria 10 IOPLL reconfiguration via MIF Streaming. Additionally, this video includes step-by-step instructions to generate MIF File For a single PLL configuration.
Use the IBIS-AMI Model to Estimate Signal Integrity of Arria 10 Transceiver	Watch this video to learn how to perform a signal integrity simulation with Arria 10 transceiver IBIS-AMI model in JNEye. Additionally, this video covers eye diagram reporting.
Creating and Running a UEFI LCD Application Part 2	This video teaches the user how to create an example LCD application on the Arria 10 Soc. The application writes a character to the LCD via the I2C interface.
Creating and Running a UEFI LCD Application Part 1	This video teaches the user how to create an example LCD application on the Arria 10 Soc. The application writes a character to the LCD via the I2C interface.
Enable UEFI DXE Phase	Watch this video to learn how to enable UEFI DXE Phase and the UEFI Shell. Additionally, learn how to boot linux from the DXE phase.
Networking Features Under UEFI Shell	Watch this video to learn how to use Ethernet features under UEFI Shell after booting to DXE Phase.
How to Run PCIe AVMM DMA Reference Design in Arria 10 Device	Watch this video to learn how to setup the PCIe AVMM DMA reference design hardware and run the it using Linux or Windows.
How To Use In-System Memory Content Editor	Watch this video to learn about the In-System Memory Content Editor. Additionally watch a step by step tutorial on using the In-System Memory Content Editor for debugging.
Cyclone V Nios II Remote System Upgrade with EPCQ	Watch this video to learn how remote configuration works. Additionally, learn how to implement a system to program EPCQ flash over Ethernet.
How to perform IOPLL Dynamic Phase Shift in Arria 10?	This is targeted for users who need to perform dynamic phase shift during in user mode, which allow user to change the output clock phase.
Debugging Techniques for Common Issues faced for Nios based Bare Metal Systems	This video outlines a dozen different techniques to solve issues engineers might face using a Nios based systems. This includes proper use of the programmer, qsys, assignments, and eclipse.
Using HPS Loaner I/O in Cyclone V and Arria V SoCs	The loaner I/O ports available in Altera SoCs allow you to reuse ports that were previously dedicated to hardened peripherals within the ARM hard processor subsystem (HPS) block.
Understanding Avalon MM Bursting	Learn what Avalon MM bursting is and how to use it in the Qsys system integration tool within the Intel FPGA Quartus II software
U-Boot Console and FDT Debug	Currently the device tree(DTB) under the HPS needs to be generated via soceds shell or the Linux build system. For some debug situations, the user can actually utilize the FDT (flattened device tree) feature under the u-boot screen which comes under the system boot.
Trace the Local Routing of CDR Recovered Clock From Transceiver	This video shows users how to perform the local routing tracing for CDR recovered clock - rx_clkout from transceiver channel to IO pin using TimeQuest and Chip Planner.
Tips to Implement Transceiver Dynamic Reconfiguration in 28-nm Devices	This video shows you how to implement different transceiver dynamic reconfiguration features in 28-nm devices. The reference design used in this video can be downloaded from the Intel FPGA Wiki page.
Streamline Profiling on Altera SoC FPGA Part 2 - Running Streamline	Learn how to compile and copy the gator daemon and driver which is needed to run the Streamline profiling tool on Intel SoC FPGAs using ARM DS-5 Intel FPGA Edition.
Streamline Profiling on Altera SoC FPGA Part 1 - Setup	Learn how to compile and copy the gator daemon and driver which is needed to run the Streamline profiling tool on Intel SoC FPGAs using ARM DS-5 Intel FPGA Edition.
Stratix V Transceiver Toolkit	This video shows users how to perform Stratix V transceiver PMA analog settings auto sweep using the transceiver toolkit.
SoCEDS Installation	This video describes how to install the SoCEDS design tools.
SoC HPS System Generation Using Qsys	How to configure and generate a basic SoC HPS (Hard Processor System) system using the Qsys system generation tool within the Quartus software targeting the Intel FPGA Cyclone V SoC Development Kit.
Simulation of SoC HPS DDR3 Core	Learn to simulate a DDR3 core from the SoC HPS (Hard Processor System) using Quartus software and the Qsys system integration tool.
Simulating a Nios II Processor Design	This video describes how to simulate the Nios II processor design.
SignalTap II Embedded Logic Analyzer Basics	See how to set up and perform a basic Intel FPGA functional design analysis with the SignalTap II embedded logic analyzer within the Quartus software!
SDI II IP Step by Step Implementation Guide for an Intel FPGA Arria 10 Device	This video demonstrates how to implement an Intel FPGA SDI II IP core in an Arria 10 device.
SDI II Dynamic TX Clock Switching Feature Implementation and Hardware Verification	This video provides theory of operation and a demonstration of the implementation of the SDI II dynamic TX clock switching capability for Arria 10 devices.
Running the SoC Preloader With the ARM DS-5 Debugger	Learn to use the ARM DS-5 Debugger with the Preloader on the Altera Cyclone V SoC Development Kit.
Quick Signal Tapping with SignalProbe in the Altera Quartus II Software	See how to quickly bring internal FPGA design signals out to unused I/O pins for debugging using SignalProbe!
Quartus Pin Migration	This video will show the user how to manually perform the device migration using excel pin out file without the Quartus II software pin migration view.
Quartus In Systems Sources and Probes Debug Flow	This video will show the user how to control any internal signal with a completely dynamic debugging environment without using any external test system.
Qsys Optimization Techniques - Part 2 of 2	This is part two of a two part video describes Optimizing Qsys systems for performance. You will be shown how to search for, identify, and reduce or eliminate adapter insertion to improve performance.
Qsys Optimization Techniques - Part 1 of 2	This is part one of a two part video describes Optimizing Qsys systems for performance. You will be shown how to search for, identify, and reduce or eliminate adapter insertion to improve performance.
Preloader and U-boot Generation for Intel FPGA Cyclone V SoC	Learn how to make the preloader and U-boot bootloader for the HPS Intel FPGA Cyclone V SoC.
PMA Analog Control Reconfiguration for Stratix V	This video shows users how to perform PMA analog control reconfiguration in the Stratix V transceiver.
PLL reconfiguration with MIF file	How to perform PLL reconfiguration with a .mif file by utilizing Intel FPGA PLL IP and Intel FPGA PLL Reconfiguration IP in Quartus.
Performing dynamic reconfiguration for the Arria 10 transceiver	This video shows users how to perform data rate changes using TX PLL switching with the embedded streamer in Arria 10 devices.
Reconfigure Arria 10 Transceivers using Embedded Streamer	This video will show users how to perform dynamic reconfiguration with the Arria 10 transceiver Standard PCS using the embedded streamer.
Optimize Intel FPGA Qsys System Performance by Manually Controlling Pipelining in the Qsys Interconnect	Learn how to obtain performance in Intel FPGA Qsys memory mapped interconnect by the use of pipelining.
OpenCL on Altera SoC FPGA (Linux Host) – Part 4 – Setup of the Runtime Environment	Setup the Altera Cyclone V SoC board to run the OpenCL example, and execute the host code and kernel on the board.
OpenCL on Altera SoC FPGA (Linux Host) – Part 3 – Kernel and Host code compilation for SoC FPGA	Compile the OpenCL kernel and host code targeting the FPGA and processor of the Altera Cyclone V SoC FPGA.
OpenCL on Altera SoC FPGA (Linux Host) – Part 2 – Running the Vector Add example with the emulator	Download and compile an example OpenCL application targeting the emulator that is built into the Altera OpenCL
OpenCL on Altera SoC FPGA (Linux Host) – Part 1 – Tools download and setup	Learn how to download, install and configure the tools required to develop OpenCL kernels and host code targeting Altera SoC FPGAs.
Migration from legacy 10G Ethernet MAC IP to the new low latency 10G Ethernet MAC IP	This video introduces the Intel FPGA Low Latency 10G Ethernet MAC IP Core and demonstrates the migration steps from the legacy 10G Ethernet MAC IP core.
MAX10 Remote System Update Part 1	This video is an overview of the Remote System Update feature in MAX10 FPGA and provides guidance on how to use the MAX10 Remote System Update reference design.
MAX10 Remote System Update Part 3	This video is an overview of the Remote System Update feature in MAX10 FPGA and provides guidance on how to use the MAX10 Remote System Update reference design.
MAX10 Remote System Update Part 2	This video is an overview of the Remote System Update feature in MAX10 FPGA and provides guidance on how to use the MAX10 Remote System Update reference design. Part III is here: https://youtu.be/r3wcgr3LmjA
MAX10 oscillator to build NIOS	The video shows how to use the MAX10 internal oscillator to reduce component count, board space and overall total cost.
Managing Messages in Quartus	This video demonstrates how to view, hide, sort, clear, and flag messages in the messages window.
Managing Custom Libraries of Qsys Components Through Multi-Layered Search Paths	This video demonstrates how to create search paths for Qsys designs, which can be leveraged across multiple users and projects, in order to create powerful libraries of custom IP components.
Making ECO changes using Intel FPGA Quartus' Chip Planner and Resource Property Editor Part 3 of 3	Learn how to make ECO changes using Intel FPGA Quartus chip planner and resource property editor.
Making ECO changes using Intel FPGA Quartus' Chip Planner and Resource Property Editor Part 2 of 3	Learn how to make ECO changes using Intel FPGA Quartus chip planner and resource property editor.
Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor Part 1 of 3	Learn how to make ECO changes using Intel FPGA Quartus chip planner and resource property editor.
LPDDR2 External Memory Controller Using Altera Cyclone V GX Dev Kit	Watch this video to learn about the LPDDR external memory controller on the Cyclone V GX development Kit.
JESD204B Demonstration	A demo of the JESD204B IOT with TI DAC and the Intel FPGA Arria V GT development kit.
Introduction to PHYLite IP	How to utilize the Intel FPGA PHYLite IP in your design.
Introduction to Nios II Gen 2 Part 2	This video introduces the Nios II Gen 2 processor in the Quartus. This video also covers the challenge of data cache vs. non-data caches in the Nios II Gen 2 processor.
Introduction to Altera Nios II Gen2 Part 1 of 2	Learn about the Nios II Gen2 features . Tour of new Qsys GUI. How to migrate Nios II to Nios II Gen 2. Using Qsys, tcl scripts. How to create a Nios II /S configuration with Nios II Gen 2 /F.
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2	This video covers the current flow for External Memory Interface placement and its complexities and how Blueprint will alleviate the problem by speeding up IO and Periphery placement. Part 2 of the video includes a BluePrint demo.
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2	This video covers the current flow for External Memory Interface placement and its complexities and how Blueprint will alleviate the problem by speeding up IO and Periphery placement. Part 2 of the video includes a BluePrint demo.
Implementing Over Constraint In Arria 10 External Memory Interface	Watch this video to learn about implementing over constraints for Arria 10.
Implementing design security feature in Altera FPGAs	This video describes security features to protect your programming image in Stratix V FPGAs.
Implementing a Partial Reconfiguration Design within Qsys for Altera FPGAs	Partial Reconfiguration enables you to dynamically reconfigure a portion of the FPGA while the rest of the design remains fully operational. Qsys is a system integration tool within the Quartus II software.
Implement Transceiver Design Using Qsys and Transceiver Toolkit	Implementing a Cyclone V GX 2G transceiver design using the TerASIC Cyclone V GX development kit.
IBIS Model With Mutual RLC Coupling	This video shows the user how to generate an IBIS model with per pin RLC and mutual coupling package information.
IBIS Model Generation	This video demonstrates how to generate IBIS models from within Quartus.
How To Use the Transceiver Toolkit Part 4	4 part video describing how to use the Transceiver ToolKit Application. This application will be demonstrated on an Arria 10 Development kit and explain how to get the optimal PMA settings for the transceiver.
How To Use the Transceiver Toolkit Part 3	4 part video describing how to use the Transceiver ToolKit Application. This application will be demonstrated on an Arria 10 Development kit and explain how to get the optimal PMA settings for the transceiver.
How To Use the Transceiver Toolkit Part 2	4 part video describing how to use the Transceiver ToolKit Application. This application will be demonstrated on an Arria 10 Development kit and explain how to get the optimal PMA settings for the transceiver.
How To Use the Transceiver Toolkit Part 1	4 part video describing how to use the Transceiver ToolKit Application. This application will be demonstrated on an Arria 10 Development kit and explain how to get the optimal PMA settings for the transceiver.
How to Use the Intel FPGA Board Skew Parameter Tool	This video will demonstrate how to use the Board Skew Parameter Tool to assist in calculating board skew parameters needed when generating Intel FPGA external memory interface IP.
How to use and navigate the rocketboards website for Open Source Linux	The video outlines the various functions of the Rocketboards website and provides an overview of how to use it effectively
How to Setup Quartus Licenses	This tutorial explains how to setup a Quartus fixed node or floating node license.
How to setup Native link for Simulation using Intel FPGA Quartus II tool	In this video you will learn How to setup Native link for Simulation using Intel FPGA Quartus II tool. The tools used in this video are Quartus II 14.1 and Modelsim-Altera SE 10.3c , you can any QII and Modelsim version.
How to program MAX II/V User Flash Memory with only a JAM file	The video shows users how to use the Quartus programmer to properly program a JAM file to MAX II/V user flash.
How to program files into the QSPI Flash on the Altera Cyclone V SoC board	This video demonstrates how a user can flash boot images onto Altera SoC board's QSPI flash device. The video covers flashing QSPI flash using quartus_hps, U-boot, and Linux tools (reside in SD card).
How to perform Transceiver rate change using TX PLL switching dynamic reconfiguration in Native PHY	This video shows users how to perform transceiver data rate changes using TX PLL switching dynamic reconfiguration in Native PHY.
How to perform data rate change with TX local divider dynamic reconfiguration in Native PHY	This video shows users how to perform transceiver data rate change through TX local divider dynamic reconfiguration in Native PHY.
How to Migrate Intel FPGA Triple Speed Ethernet to Arria 10 Devices in Quartus Software	This video demonstrates how to migrate IP cores to the Arria 10 FPGA family using the Triple Speed Ethernet as an example.
How to Migrate a Quartus II Project to a Different Altera Device	This is a demonstration on how to set up an Altera Quartus II project for potential migration to a different device. See how to migrate a current project using one device to a different sized device and confirm that the existing pinouts are preserved.
How to merge TX PLLs NativePHY	This video will show how to merge the TX PLLs of two Stratix V Native PHY instances with TX PLL reconfiguration enabled by using the TX PLL reconfiguration group assignment.
How to Measure TX Jitter for PRBS23 at 10.3125Gbps Using Lecroy RTS	This video shows users how to measure TX jitter for a PRBS23 data pattern at 10.3125Gbps using a Lecroy Real Time Scope (RTS).
How to manually constrain the Arria 10 ATX PLL location using Assignment Editor and Chip Planner	Watch this video to learn how to manually constrain the Arria 10 ATX PLL location using the Assignment Editor and Chip Planner.
How to interoperate TI DAC37J84 with Altera JESD204B MegaCore on Stratix V FPGA	Watch this video to learn about Interoperability with the JESD204B Stratix V IP core and Texas Instruments DAC37J84.
How to interoperate ADI AD9680 with Altera JESD204B IP Core on Stratix V FPGA	Step by step guide to set up the hardware, configure the analog-to-digital converter, and configure Intel FPGA JESD204B IP core.
How to Interface to DDR3 Memory Using Altera UniPHY EMIF IP	Watch this video to learn how to implement UniPHY EMIF IP.
How to implement the link test with LVDS DPA in soft-CDR mode	This video will covers the required IP, configuration, and In-System Source and Probe (ISSP) to facilitate LVDS link real time debugging.
How to Export MAX 10 ADC Conversion Data to the Core for Post-Processing	Watch this video for a step by step guide on exporting MAX 10 ADC conversion data to the FPGA core for post-processing.
How to efficiently map shift register elements into IntelFPGAs	This video shows how to effectively map shift register or SRL elements into Arria 10 or Stratix V registers, MLABs, or Block RAMs using VHDL RTL code.
How to Design Power Trees with PowerPlay Power Tree Designer	This video will teach you how to use Altera's online powerplay power tree designer tool step by step. This video will show which Enpirion power modules are required for an efficient power tree design.
How to Debug Intel FPGA Triple Speed Ethernet Link Synchronization Issue	Watch this video to learn about debugging triple speed Ethernet link synchronization issues.
How to Debug Altera Triple Speed Ethernet Auto Negotiation Issue	Learn to use auto negotiation for synchronization of Ethernet peripherals.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2	Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1	Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to create simultaneous measurement with Max 10 ADC Part 2	This video explains the differences between Max 10 ADC IP and demonstrates how to create a simple simultaneous ADC measurement.
How to create simultaneous measurements with Max 10 ADC Part 1	This video explains the differences between Max 10 ADC IP and demonstrates how to create a simple simultaneous ADC measurement.
How to Create ADC Design in MAX 10 Device Using Qsys Tool	This video will demonstrate how to create the ADC design in MAX10 devices using the Qsys system integration tool within the Quartus II software and how to use the ADC toolkit to view the measured analog signal
How to create a State Machine with the Quartus State Machine Wizard	Using a traffic light controller as an example, this video will take you through the steps to create a state machine with the Quartus II State Machine Wizard.
How To Automate The External Memory Interface Test Through Quartus Scripting	Watch this video to learn how to automate common processes using External Memory Interface IP.
Hard Processor System implementation with custom interconnect in an Altera SoC	This video shows how to extend the HPS (Hard Processor System) with custom interconnect to be implemented in the SoC. It demonstrates how the Qsys system integration tool within the Quartus II software is used without Qsys interconnect.
Getting Started with OpenCL part 5	This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT, on the Cyclone V SoC using a Windows machine.
Getting Started with OpenCL Part 4	This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT, on the Cyclone V SoC using a Windows machine.
Getting Started with OpenCL part 3	This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT, on the Cyclone V SoC using a Windows machine.
Getting Started with OpenCL part 2	This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT, on the Cyclone V SoC using a Windows machine.
Getting Started with OpenCL part 1	This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT, on the Cyclone V SoC using a Windows machine.
Getting Started with Linux on the Altera Cyclone V SoC Board	Learn how to boot the Cyclone V SoC using prebuilt Linux images from rocketboards.org. Learn about the Adeneo partnership with Altera and Adeneo Embedded.
Generation of ISC file for MAX10 IEEE 1532 Programming	Watch this video to learn how to generate the In System Configuration file by using Serial Vector Format and a TCL script. Additionally, learn how to modify the content for ISC on User Flash Memory.
Generating a test bench with the ModelSim simulation tool	This video will provide the easiest way to generate a test bench with Modelsim. You can modify the test bench with VHDL/ Verilog programming in the test bench generated.
From Qsys to Quartus	This video walks through the creation of a system in Qsys, what files are generated, how to pull those files into Quartus, advantages/disadvantages of various design flows (.qip vs .qsys, qsys as the top level vs- as a design block), and timing constraints for an Intel FPGA
FPGA Version Control Part 2	Watch this video to learn about different methods for implementing version information in an Intel FPGA, use of memory resources, an example project with ROM IP, and the memory initialization file (mif).
FPGA Version Control Part 1	Watch this video to learn about different methods for implementing version information in an Intel FPGA, use of memory resources, an example project with ROM IP, and the memory initialization file (mif).
Finding and Using Reference Designs in the Intel FPGA Design Store (part 2)	This video will show you how to find and use reference designs in the Intel FPGA Design Store.
Finding and Using Reference Designs in the Intel FPGA Design Store (part 1)	This video will show you how to find and use reference designs in the Intel FPGA Design Store.
Fast Forward Compile	This video demonstrates the Quartus Fast Forward Compile feature which predicts the timing benefits of hyper-pipelining using the Stratix 10 family of FPGAs.
External Memory Interface Driver margining Part 2	This video describes the External Memory Interface (EMIF) Driver Margining feature introduced in Quartus version 15.1.
External Memory Interface Driver margining Part 1	This video describes the External Memory Interface (EMIF) Driver Margining feature introduced in Quartus version 15.1.
Design a Qsys System Using the Nios II processor SD Card Interface	This video demonstrates two applications showcasing an Intel FPGA Nios II processor SD card interface.
Debug PLL loss of lock	This how-to video discusses techniques for debugging a PLL loss of lock condition on Intel FPGAs.
DDR4 Ping Pong PHY	Watch this video to learn what a Ping Pong PHY is and about its benefits. Additionally, learn to analyze ModelSim simulation results.
DDR Termination using Intel FPGA EV1320 devices	This short video on DDR termination will show you how you can save 1 Watt or more on your termination circuitry using Intel FPGA Enpirion devices.
Creating Multiple Arria 10 Memory Designs with Qsys	This video will demonstrate how to create an Arria 10 Qsys design with multiple Arria 10 External Memory Interface IP or EMIF example designs.
Creating Custom Qsys Components with the Qsys Component Editor	Learn how to use the Component Editor to turn a custom HDL design into a Qsys-compatible system component.
Create your first Verilog based blinking LED with MAX 10 evaluation kit (Part 3)	Watch this video to learn about Quartus, FPGAs, and Verilog. Additionally, create a project that blinks a LED using a MAX10 evaluation kit.
Create your first Verilog based blinking LED with MAX 10 evaluation kit (part 2)	Watch this video to learn about Quartus, FPGAs, and Verilog. Additionally, create a project that blinks a LED using a MAX10 evaluation kit.
Create your first Verilog based blinking LED with MAX 10 evaluation kit (Part 1)	Watch this video to learn about Quartus, FPGAs, and Verilog. Additionally, create a project that blinks a LED using a MAX10 evaluation kit.
Configuring HPS Bridges in Intel FPGA SoCs	Watch this video to learn about properly configuring HPS bridges using the MegaWizard. Additionally, learn about the characteristics of each bridge and when to use them.
Configuring Altera MAX 10 User Flash Memory	This video demonstrates how to configure the User Flash Memory (UFM) in a MAX 10 FPGA device.
Combining a Nios II ELF executable into a Hardware Project SOF file	This video provides a step-by-step guide on how to integrate a NIOS II software project executable ELF image into a Quartus II hardware project SOF file.
Chip Planner Instructional Video 2	Part 2 of 2 video on Chip Planner Birds Eye view, routing utilization, design element search, and logic lock view and creation.
Chip Planner Instructional Video 1	Part 1 of 2 on Quartus Chip Planner. Watch this video to learn about cross referencing timing paths, fanin, fanout, routing delay, and clock regions.
Cascading PLL Counters to achieve synthesized clock frequencies	Watch this video to learn how to synthesize low frequency output with Altera PLL IP core via output counter cascading.
Board Timing For Arria 10 EMIF IP	This video shows how to fill up the board timing tab. Additionally, the video explains Intel FPGA’s external memory interface (EMIF) simulation guidelines.
Automated Check of Intel FPGA External Memory Interfaces Board Layout Guidelines	This video explains how to use Intel FPGA developed rules within Mentor Graphics' HyperLynx DRC tool to automatically check board layout guidelines.
Arria10 Configuration via Protocol (CvP)	This video demonstrates how to configure your Arria 10 device using the PCIe protocol.
Arria 10 SoC Authentication and Crypto Flow	This video demonstrates the tool flow used to authenticate and encrypt the boot loader and programming files on an Arria 10 SoC FPGA device.
Arria 10 interface to ADI 9144 using JESD204B IP	Watch this video to learn about the ADI AD9144 with Altera JESD204B IP core. The demonstration uses Intel FPGA’s JESD204B TX IP core interoperating with Analog Devices (ADI) digital-to-analog converter (DAC) AD9144 @ 9.8304Gbps using Arria 10 FPGA Development Kit.
Arria 10 Hybrid Memory Cube Controller Demo part 2 of 2	This video shows a hardware demonstration of the Arria 10 Hybrid Memory Cube Controller at 15 Gbps showcasing the latency and bandwidth of this interface.
Arria 10 Hybrid Memory Cube Controller Demo part 1 of 2	This video shows a hardware demonstration of the Arria 10 Hybrid Memory Cube Controller at 15 Gbps showcasing the latency and bandwidth of this interface.
Arria 10 External Memory Interface Toolkit	This video describes the features and options of the Intel FPGA Arria 10 External Memory Interface (EMIF) toolkit.
Arria 10 External Memory Interface Read and Write 2-D Eye Diagram	This video shows which IP settings are important for Arria 10 External Memory voltage references. Additionally, this video demonstrates how to enable and generate read write eye diagrams for each DQ pin.
Arria 10 EMIF Example Traffic Generator	Watch this video to learn how to implement different test patterns on the Arria 10 traffic generator for external memory interface.
Intel FPGA Wireless Application on Remote Fault Identification and RRH Spectrum Monitoring	Demonstration of Intel FPGA's wireless solution on Remote Fault Identification and RRH Spectrum Monitoring using theory introduction and real demos.
Intel FPGA Transceiver Loopback With In-System Sources and Probes	Watch this video to learn how to enable the internal serial loopback of Intel FPGA’s Custom PHY using In-System Source and Probe (ISSP).
Intel FPGA SoCs Booting from FPGA	Step-by-step demonstration of how to boot the Intel FPGA Cyclone V SoC Development Kit by using a Preloader stored in the FPGA fabric.
Altera RF Framework	This video describes the seven components of Intel FPGA's RF framework for rapid prototyping of the digital front end in remote radio head applications using Matlab, Simulink, and DSP Builder.
Altera Phylite Demo Part 2	Watch this video to learn how to compile the Altera PHYLITE DEMO design. Additionally, learn to perform dynamic configuration with NIOS-II.
Altera Phylite Demo Part 1	This video explains the high level architecture of the Altera PHYLITE DEMO design. Additionally, interaction between PHYLITE-IN, PHYLITE-OUT, Traffic Generator, and NIOS-II processor is explained.
Intel FPGA JESD204B IP Quick Start Video	Learn about JESD204B and the Altera JESD204B IP solution, and find out how you can easily create an example design that works on hardware.
Intel FPGA Design Assistant FPGA Design Rule Checking Design Tool	This video shows a basic overview of the Quartus Design Assistant design rule checking feature and how to understand the warning messages to produce higher quality and reliable FPGA designs.
AN739 Demonstration of Altera 1588 System reference design	Watch this video to learn about Intel FPGA’s new 1588 system level reference design (AN739) using both Hardware IP ( 10G Ethernet MAC with 10G BaseR PHY) and software ( PTP stack LinuxPTPv1.5, a preloader, 10G-bps Ethernet MAC driver and a PTP driver)
Active Serial Configuration via JTAG	Watch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core.
Accessing UNIPHY Calibration Data	Watch this video to learn how to access the calibration data for Altera's UNIPHY external memory interface and determine the memory mapped address for calibration data.
JESD204B IP Quick Start Video	Learn about JESD204B and the Intel FPGA JESD204B IP solution. Additionally, find out how you can easily create an example design that works on hardware.
Push button hardware design examples in Quartus Prime	Need a fully functional hardware design ASAP? In the Quartus Prime design software, it’s as easy as pushing a button! With Altera’s new out-of-the-box dynamically generated design examples, you can now customize, generate, compile, and hardware verify a fully functional design in less than two hours!
Introducing the External Memory Interface traffic generator	This video will show you how to enable the traffic generator 2.0 during external memory interface IP generation, how to configure the traffic generator in the external memory interface toolkit, and some use-cases where this new traffic generator can come in handy during debug.
How to Debug Triple Speed Ethernet	Watch this video to learn about debugging triple speed Ethernet.
Board Management Controller - Part 2	Watch this video to learn about the board management controller. The board management controller allows users to control PM Bus based power module.
Introduction to Driver Margining Features	Watch this video to learn what the driver margining tools are and how to use them.
External Memory Interface Traffic Generator Part 2	This video will show you how to enable and configure the traffic generator 2.0. Additionally, this video demonstrates use-cases where the traffic generator can be handy during debug.
Automated generation of predefined SignalTap II Files for Arria 10	Watch this video to learn about generating predefined SignalTap files for IP cores that match your design hierarchy.
How to order Enpirion Samples	Learn a simple way to order Intel FPGA Enpirion samples.
Arria 10 Hard Floating Point DSP Demonstration	Watch this video to learn about the Arria 10's hard floating point DSP block architecture, capabilities, and advantages. Additionally, learn about migration from soft DSP to hard DSP using the DSP builder.
Board Management Controller - Part 1	Watch this video to learn about the board management controller. The board management controller allows users to control PM Bus based power module.
Dynamic Reconfiguration of an Arria 10 Transceiver	Watch this video to learn how to perform data rate changes using TX PLL switching and embedded streamer in Arria 10 devices.
How to interoperate ADI AD9680 with Altera JESD204B IP on Stratix V	This video includes a step by step guide to configure the analog-to-digital converter, Intel FPGA JESD204B IP core, and set up the hardware.
External Memory Interface Traffic Generator Part 3	This video will show you how to enable and configure the traffic generator 2.0. Additionally, this video demonstrates use-cases where the traffic generator can be handy during debug.

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