- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... The Max Deskew (Cycles) in Table 3-1 of the SerialLite II IP Core ... 4 then the
Maximum Deskew time accepted by transceiver is 2 tx_coreclock clock ...
... solutions >Why the SerialLite II (SLII) core failed to link up intermittently? ... Why
the SerialLite II (SLII) core failed to link up intermittently? ...
... Why are corrupted data packets received at the Atlantic user interface when
Retry-on-error option is enabled for priority packets in SerialLite II. ...
... Last Modified: July 01, 2014. IP Product: Renewal SerialLite. Do the SerialLite
II Design Examples on altera.com support VHDL? Description. ...
... Why does the SerialLite II unidirectional variant fail to load in simulators when
targeting Stratix GX using Quartus® II 5.1 or Quartus II 6.0? ...
... Incorrect Port Direction for SerialLite II IP Core Targeting Arria V, Cyclone
V, and Stratix V Devices. Description. The SerialLite ...
... solutions >SerialLite II IP Core Still Displays Unsupported Devices in GUI. ...
SerialLite II IP Core Still Displays Unsupported Devices in GUI. ...
... SerialLite II IP Core High Priority Packets Corrupted During High Traffic
Conditions. Description. For SerialLite II IP core ...
... Timing Violations when tx_rdp and rx_rdp Clocks are Not Synchronized
to Core Clock in SerialLite II IP Core. Description. ...
... Why can't I generate the Arria 10 device SerialLite III design example in Quartus
Prime Standard editions 16.0, 16.1 and 17.0? Description. ...