Existing users of the 10GbE MAC IP core can migrate to the Low Latency Ethernet 10G MAC IP core with minimal modifications on the system. However, it is important for you to understand the differences between these two IP cores before proceeding with the migration. This document describes the differences of both the MAC IP cores and provides the migration steps from 10GbE MAC IP core to Low Latency Ethernet 10G MAC IP core.
As a summary, there are multiple major differences between 10GbE MAC IP core and Low Latency Ethernet 10G MAC IP.
|Features||Low Latency 10G Ethernet MAC IP core||10GbE MAC IP core|
|Supported Device||Arria 10, Arria V GZ, Stratix V||Cyclone, Arria, and Stratix devices except Arria 10 1|
|MAC Latency (TX + RX)||
|Avalon Streaming (Avalon-ST) Interface Data width||32-bit, 64-bit||64-bit|
|XGMII Interface Data width||32-bit, 64-bit||64-bit|
||Starting address 0x000|
|ECC detection and correction||Available||Not Available|
|Features||Low Latency Ethernet 10G MAC IP Core||10GbE MAC IP core|
|Multispeed operation (10M/100M/1G/10Gbps)||Yes||Yes|
|64-bits Avalon-Streaming (Avalon-ST) interface||Yes||Yes|
|32-bits Avalon-ST interface||Yes||—|
|64-bits XGMII PHY interface||Yes||Yes|
|32-bits XGMII PHY interface||Yes||—|
|GMII and MII PHY interface||Yes||Yes|
|Optional IEEE 1588v2 features||Yes||Yes|
|Optional statistic collections for transmit and receive datapaths||Yes||Yes|
|Optional ECC correction and detection||Yes||—|
|Compliant to IEEE 802.3 – 2008 specification||Yes||Yes|
- 32-bits Avalon-ST interface and 32-bit XGMII PHY interface for reduced pin count.
- ECC correction and detection for all internal RAMs that reside in the MAC. This is to provide status on single bit data correction and multi bit error data detection in the RAM that is impacted by electrical or magnetic interference.
These three modules are:
- 64-bit Avalon-ST adapter for both TX and RX datapaths
- 64-bit Avalon-MM adapter
- 64-bit XGMII adapter for both TX and RX datapaths
The Avalon-ST adapter converts 32-bit datapath from the MAC to 64-bit datapath to the user interface while the Avalon-MM adapter converts the register mapping of the Low Latency Ethernet 10G MAC IP core to the 10GbE MAC IP core register mapping. This register mapping conversion enables existing users of the 10GbE MAC IP core to migrate to the Low Latency Ethernet 10G MAC IP core without any software modification.
However, you are required to supply 156.25 MHz of transmit and receive clock to the Low Latency Ethernet 10G MAC when the 64-bit Avalon-ST adapters, Avalon-MM adapter, and 64-bit XGMII adapters are enabled in the IP core.
The Low Latency Ethernet 10G MAC IP core provides reset signals for the TX datapath, RX datapath, and register configuration path. The reset signal for TX datapath resets both the 312.5 MHz and 156.25 MHz clock domains. The same applies for the RX datapath. Refer to the Low Latency Ethernet 10G MAC IP user guide for more description on the reset signals for this IP core.
If the Low Latency Ethernet 10G MAC IP core with 64-bit Avalon-ST adapter, 64-bit Avalon-MM adapter, and 64-bit XGMII adapters are enabled, you may observe these additional signals in the IP core:
For the Low Latency Ethernet 10G MAC IP core instantiation without enabling any adapters, you may observe these signal names in the IP core:
- 10-bit csr_address
- 32-bit Avalon_st_tx_data
- 2-bit Avalon_st_tx_empty
- 32-bit Avalon_st_rx_data
- 2-bit Avalon_st_rx_empty
- 32-bit xgmii_tx_data
- 4-bit xgmii_tx_control
- 32-bit xgmii_rx_data
- 4-bit xgmii_rx_control
Altera recommends that you follow this migration flow.
- Select and instantiate the Low Latency Ethernet 10G MAC IP core from the MegaWizard Plug-In Manager or IP Catalog.
- In the Low Latency Ethernet 10G MAC parameter editor, select the same MAC variant used in the existing 10GbE MAC IP core in the user system design.
In the Low Latency Ethernet 10G MAC parameter editor, turn on the following
parameters to enable all the adapters in the MAC interface:
- For Quartus II version 14.1 or before: Under 64-bit Ethernet MAC Interfaces, select Use 64-bit Ethernet 10G MAC XGMII Interface , Use 64-bit Ethernet 10G MAC Avalon Memory-Mapped Interface and Use 64-bit Ethernet 10G MAC Avalon Streaming interface.
- For Quartus II version 15.0 onwards: Under Legacy Ethernet 10G MAC Interfaces, select Use legacy Ethernet 10G MAC XGMII Interface , Use legacy Ethernet 10G MAC Avalon Memory-Mapped Interface and Use legacy Ethernet 10G MAC Avalon Streaming interface.
- Click Finish or Generate to generate all the necessary files to synthesize the IP core.
- Instantiate a separate 312.5 MHz clock from any existing PLL in the design.
Connect this clock source to tx_312_5_clk and rx_312_5_clk
Both clock signals can share the same clock source.
After generating the synthesis file for the Low Latency Ethernet 10G MAC IP core, you can replace the existing 10GbE MAC IP core synthesis file (<user_specified_ip_filename> .v) with the newly generated Low Latency Ethernet 10G MAC synthesis file. Due to the differences in the signal names between both cores, you must make sure these signals are connected correctly to the user and PHY interfaces.
|Low Latency Ethernet 10G MAC IP Signal Names||10GbE MAC IP Core Signal Names|
|May 2015||2015.05.04||Initial release.|