At the Intel SoC FPGA Developer Forum (ISDF), you’ll gain technical insights into your next designs based on SoC FPGAs.  At the heart of the event are technical sessions presented by industry experts you won’t find anywhere else. 

 

Keynote

ISDF San Francsico Keynote from Intel CEO Brian Krzanich

Hear about the evolution and transformation of the smart and connected world and the importance of SoC FPGAs in that world.

Tracks

Hardware: Hardware and software developers are facing an ever-changing, connected world.  Intel is uniquely positioned to support developers with a portfolio of heterogeneous solutions that span across the data center, network infrastructure and Internet of Things (IoT).  This track will discuss a comprehensive vision of Intel connecting the world from the sensor to the data center and back from a performance, power, cost, security and energy efficiency standpoint.

Hardware Hands-on Session:  Discuss and use the tools and metholodogy necessary to design an SoC FPGA-based system.  The session includes understanding and configuring the features of the Hard Processor System (HPS), creating and generating an SoC system using the Qsys system integration tool and SoC FPGA debugging tools and methodology.  The session is repeated twice during the day, but, due to the hands-on nature of the course, space is limited.  (Each sessoin covers the same material, so you only need to attend one.)

Software: Find out how easy it is to leverage the power of FPGA custom hardware to accelerate software code execution. Learn how to Increase productivity and reduce development time, along with advanced code optimization and debug techniques.

Software Hands-On Session: Attendees will boot and use Linux on an SoC FPGA board, try out some debugging and analysis tools, interact with the FPGA, download and run bare-metal examples.  The session is repeated twice during the day, but, due to the hands on nature of the course, space is limited. (Each session covers the same material, so you only need to attend one.)

 

Click on the agenda table below for a larger view.

Call for Submission

The ISDF 2016 Call for Submissions for North America and Europe is now closed.  Thank you for the submissions, accepted papers have been notified.

To submit a presentation for consideration for Japan or Asia Pacific, please submit an abstract by August 31, 2016 by sending an email to:  isdf_content@altera.com

Your abstract should contain:

  1. Author/Speaker
  2. Session Title
  3. Designate HW or SW track
  4. Description (200 words or less)
  5. Include any supporting reference material (system block diagrams, photos, charts, performance data, etc.)

What we are looking for:  A 20-minute presentation that presents insights on an application challenge and how SoC FPGAs uniquely address the challenge, speed up the development process or give the product a competitive market edge.  It cannot be a product pitch.  Content will be reviewed by the ISDF Technical Content Committee for approval.  Accepted Abstracts will be notified by September 15, 2016

By submitting a paper to ISDF, you agree to the following terms and conditions.

Software Session Abstracts


Architecting and Developing Software on SoC FPGAs

Presentation: Configurable Embedded Systems -Trends and Technologies using SoC FPGA Multi-Core Architectures, Victoria Mitchell, Intel Programmable Solutions Group

This session analyzes system software architecture trends and technologies for integrated processor and field-programmable gate array (FPGA) systems. We will focus on using embedded Linux, real-time operating systems, and bare-metal programming for single-core, symmetric multiprocessing (SMP), and asymmetric multi-core (AMP) multi-core configurations.

  • Bare-metal and embedded operating system options
  • SMP/AMP multi-core software architectures
  • Virtualization and hypervisors including Kernel-based Virtual Machine (KVM)

Presentation:  Heterogeneous Multicore OpenAMP, Felix Baum, Mentor Graphics

  • There is a significant and growing trend  toward heterogeneous multicore systems which promise increased system performance while still conforming to tight power budgets. For example, Altera SoC FPGA systems typically combine a hard dual-core ARM Cortex-A9 processor with any number of Nios II soft processors in the FPGA fabric. Running multiple operating systems in systems like these creates new and interesting challenges for system architects. This session will present the OpenAMP standard, opportunities it provides for system partitioning and consolidation, typical use cases, and design considerations for architecting and developing software on multicore systems.

Presentation:  Virtual Prototyping for Intel® SoC FPGA-based Hardware and Software Development, Joe Hamman, Mentor Graphics

  • This session will overview the effective approach of Virtual Platforms and explain how many of the problems that occur when using physical hardware are solved: full visibility, powerful control, and non-intrusive trace analysis to create a deterministic and scalable environment. With this approach, issues in the system can be found earlier in the design lifecycle and resolved.

Using SoC FPGAs for Software Acceleration and Offload

SoC FPGAs can offload the processor by accelerating specific workloads, and have the flexibility to adapt to changing interface standards.  This session will examine application examples for accelerating software using FPGA hardware.

Presentation:  Lessons from the Spaceship for the Sedan, Daniel Noal, Wind River Systems

  • In order for autonomous driving to become mainstream, a vehicle must intelligently gather relevant data and communicate not only within its own complex vehicle systems but with the external world. In particular, advanced driver assistance systems (ADAS) must rely on reliable automotive application software on image recognition SoC platforms in order to accurately capture necessary information to make autonomous driving-related decisions. We'll examine the intricacies of autonomous driving, especially around technologies to ensure safety, that must be addressed in order to bring it to the real world.  

Presentation:  Customizable Graphics Acceleration, Thomas Hase, TES

  • Today's platforms have graphics requirements for modern, smartphone-like HMIs and enabling frameworks like Qt*, WebGL* and Android*. This presentation reviews those requirements, including a comparison of Open GL ES 2.0 and 3.1.  It then introduces a complete Qt 5.x system solution for Altera Cyclone V SoCs using a fully OpenGL ES 2.0/3.1 and VULKAN* compliant graphics rendering core and explains how to install and integrate it.

Presentation: Wireless Workload Acceleration using SoC FPGAs, Xiaohan Chen, Intel PSG Wireless Business Division

  • Offloading key portions of the algorithm to the FPGA and the use of hardened floating-point DSP blocks can deliver significantly improved performance.  This session will examine the implementation of wireless remote radio head (RRH) digital pre-distortion (DPD) algorithm acceleration using FPGA hardware acceleration and the peformance improvement, power and space savings of using these techniques.

System Software Architectures for Hardware/Software Co-Development

Traditionally, designers create field-programmable gate array (FPGA) applications using hardware description languages such as VHSIC Hardware Description Language (VHDL) and Verilog* HDL.  This session will examine other high-level methods to develop and program system on a chip (SoC) FPGAs that enhance design team productivity and system performance.

Presentation:  Power Efficient Acceleration using Intel SoC FPGAs, Bill Jenkins, Intel Programmable Solutions Group

  • Parallel processing using OpenCL*provides performance improvement with power efficiency
  • Convolutional Neural Network (CNN) application examples

Presentation: Targeting SDR Systems to hardware using Intel SoC FPGA development boards with Model-based Design, Eric Cigan, MathWorks

  • Case study featuring a workflow based on MATLAB* and Simulink* for development of software-defined radio (SDR) algorithms. The workflow enables teams to use SDR hardware based on Intel SoC FPGAs and Analog Devices RF transceivers.

Security with Software

This session will investigate methods for enhancing system security using software, including:

  • Secure boot methods for SoC FPGAs
  • Building a secure, connected IoT device with real-time operating system (RTOS)
  • Technologies for securing SoC FPGAs using embedded Linux*

Presentation: SoC FPGA Secure Boot, Rodney Frazer, Intel Programmable Solutions Group

  • This presentation discusses the secure boot environments provided by the Cyclone® V SoC FPGA device family and the Arria® 10 SoC FPGA device family.  Reviews the standard boot flow and secure boot flows that are available in each family as well as the development tools that provide access and enable these capabilities.

Presentation: Building Secure, Connected, RTOS-based IoT Devices, Michel Chabroux, Wind River

  • Real-time Operating System (RTOS) devices have always played a critical role when strict performance and reliability requirements were necessary. In today’s connected world with a rapidly growing base of IoT devices, the need for security, safety certification, scalability and virtualization is expanding from optional requirements needed by select industries to a mandatory requirement of all industries when creating next-generation devices. Learn how to fulfil these requirements for today’s intelligent and connected devices.

Presentation: Technologies for Securing Intel® SoC FPGAs using an Embedded Linux* System, Iisko Lappalainen, MontaVista Software

  • This presentation will discuss the need for security, including common hacks and new attack vectors, and how to protect against them when using an embedded Linux system.  Building in security using root of trust and integrity management will be examined. Remote attestation in Network Functions Virtualization(NFV) system clusters and signed over-the-air (OTA) updates in Internet of Things (IoT) use cases are provided to illustrate protective measures.

SoC Software Development Lab

In this hands-on workshop, we will discuss the tools and methodology necessary to boot and develop software on a SoC FPGA system. We will practice creating and debugging software on a SoC development board.

Topics include:

  • Boot and use Linux* on the development board
  • Use debugging and analysis tools
  • Interact with the FPGA
  • Download and run bare-metal examples

Hardware Session Abstracts


Enabling the IoT Vision: Data Center to Edge

Presentation: Enabling the IoT Vision: Data Center to Edge, Ian Land, Intel Data Center Group, Mike Fitton, Intel Programmagle Solutions Group Wireless Business Divtion, Joerg Bertholdt, Intel Programmable Solutions Group Industrial Business Division

Hardware and software developers are facing an ever-changing, connected world.  Intel is uniquely positioned to support developers with a portfolio of heterogeneous solutions that span across the data center, network infrastructure and Internet of Things (IoT).  This session will provide a comprehensive vision of how the combination of Intel FPGA and processor connects the world from the sensor to the data center and back.

  • Heterogeneous solutions with end-to-end span
  • Data center acceleration
  • Networking and access acceleration
  • IoT acceleration and connectivity

Advances in SoC FPGA Security

Security is an increasingly important demand in today's interconnected world.  This session will examine:

  • Taxonomy of security threats
  • Intel SoC FPGA security features and roadmap
  • Secure boot methods

Presentation: SoC FPGA Hardware Security Requirements and Roadmap, Ryan Kenny, Intel Programmable Solutions Group

  • This presentation sets forth a taxonomy of security threats for FPGA and SoC FPGA end markets, then examines the Intel® SoC FPGA security feature roadmap to help protect against these threats.

Presentation: SoC FPGA Secure Boot, Rodney Frazer, Intel Programmable Solutions Group

  • This presentation discusses the secure boot hardware capabilities of the Cyclone® V SoC device and the Arria® 10 SoC device.  It then discusses the typical boot model of Cyclone V SoC and then how it can be secured by leveraging the FPGA fabric on the device.  Lastly, it will discuss the additional hardware facilities provided by the Arria 10 SoC devices.

 


Performance Optimization

This session will examine the use of hardware acceleration for improving system performance from the standpoints of networking performance and latency/real-time response.

Presentation: Hardware-Software Partitioning in SoC FPGAs: Enhancing Real-Time Performance, Guy Irving, Macnica Americas

  • When acceleration is discussed in the context of processors, this usually refers to increasing metrics of computations per second or computational throughput.  However, when dealing with real-time systems, latency and determinism are often more critical metrics, and custom hardware can be used to speed up response time and decrease system “jitter.”   This presentation discusses the methods and advantages of separating latency critical functions through a hardware/software partitioning case study of Industrial Ethernet. 

Presentation: Edge Computing - A Part of IoT, Hidenori Yakushiji, Fujisoft

  • In recent years, “IoT” started as a buzzword for adding sensors in all “connected things" and for streaming the sensed data  to the cloud. Storing, analyzing and making practical use of the data are all encompassed and underway with IoT. Today, we are facing a critical juncture on how to handle explosive growth of sensor data, day by day. This presentation will introduce the advantages of “Edge Computing” based on SoC FPGAs that includes an effective data cleansing solution for filtering the meaningful data to be sent to the cloud.

Innovate with SoC FPGAs

This session examines innovative SoC FPGA-based applications, including:

Presentation: Industrial IoT motor control trajectory optimization, Randall Restle, Digi-Key

  • Performance of servomotor-based machines is generally compromised due to poorly chosen motion trajectories and this problem is compounded when multiple axes of motors must be coordinated. The correct trajectories are cumbersome to generate and burdensome to evaluate in real-time, but these are not issues for SoC FPGAs; half of the problem is well-suited to a processor while the other half suits FPGA hardware.  Once a sophisticated trajectory generator is integrated, communication bandwidth between distributed controllers is reduced and synchronization and coordination is aptly done over pervasive, secure wireless or wired Ethernet networks.  This presentation describes such a trajectory generator solution.

Presentation: Flying with Intel® SoC FPGA: Smart Drones Enabled by Open Source Platform, Zongbo Wang, Aerotenna

  • The future of unmanned aerial vehicle (UAV) platforms is expanding, requiring faster processor speeds and flexible architectures while also providing more inputs and outputs to support additional hardware modules and sensors. This presents many challenges in today’s UAV market, because most of the platforms are designed based on the traditional micro-controller unit (MCU)due to its low cost and trivial development environment. However, for complicated applications like image data processing, theMCU‐based controller is unable to handle the complex data processing tasks and will dramatically degrade the performance of the embedded system.
  • The team at Aerotenna has designed a revolutionary, open source UAV platform - the Octagonal Pilot On Chip (OcPoC) - based on the Altera Cyclone V SoC to address these increased market needs.
  •  The OcPoC flight control platform also supports Aerotenna’s microwave based altimeter, and a 360 degree collision avoidance radar.

Presentation: Optimizing e.MMC Memory on Intel® SoC FPGA Platforms, Justin Hunter, Micron Technology

  • Managed NAND devices, like e.MMC, provide not only industry standard features and characteristics but also detailed proprietary features for monitoring health status. Though these managed NAND devices are designed to be as drop-in ready as possible, many of its features are often under-utilized.  With a little investment in software design, significant performance and data reliability improvements can be made.  This presentation will cover the best practice methods on how to optimize data throughput, improve data reliability, and increase life span capabilities of the e.MMC memory on Altera SoC platforms.

SoC Hardware Design Lab

In this hands-on workshop, we will discuss the tools and methodology necessary to design and verify a SoC FPGA system. We will practice creating and debugging a SoC system on a SoC development board.

Topics include:

  • Understanding and configuring the features of the hard processor system
  • Creating and generating a SoC system using the Qsys* system integration tool
  • Using SoC debugging tools and methodology