DSP Builder for Intel® FPGAs is a digital signal processing (DSP) design tool that allows push-button HDL generation of DSP algorithms directly from MathWorks® Simulink environment. This tool allows you to design algorithm, set desired data rate, clock frequency, and device offering accurate bit and cycle simulation, synthesizing fixed- and floating-point optimized HDL, auto-verify in ModelSim*- Intel FPGA software, and auto-verify/co-simulate on hardware. This tool adds additional Intel® libraries alongside existing Simulink libraries with the DSP Builder Advanced Blockset and DSP Builder Standard Blockset. Our recommendation is to use DSP Builder Advanced Blockset for new designs, not DSP Builder Standard Blockset except as wrapper for Advanced Blockset. 

Features:

  • Go from high-level schematic into low-level optimized VHDL targeted for Intel FPGAs
  • Perform high-performance fixed- and floating-point DSP with vector processing, such as complex IEEE 754 single-precision floating point
  • Push-button migration of design to Intel's hard floating-point DSP block in Arria® 10 and Stratix® 10 devices
  • ALU folding to build custom ALU processor architectures from a flat data-rate design
  • High-level synthesis optimizations, auto-pipeline insertion and balancing, and targeted hardware mapping
  • Flexible ‘white-box’ fast Fourier transform (FFT) toolkit with open hierarchy of libraries and blocks for users to build custom FFTs
  • Use a designer-specified system clock constraint to automatically pipeline, time-division multiplex/fold, and close timing
  • Access advanced math.h functions and multichannel data
  • Generate resource utilization tables for all designs without a Quartus® Prime software compile
  • Automatically generate projects or scripts for the Quartus Prime software, TimeQuest, Qsys, and ModelSim*-Intel FPGA Edition
 
MathWorks® tools required: MATLAB/Simulink®, Fixed-Point Designer (sold separately)

High-performance floating-point FFTs  (Arria 10 device ) 

FFT Size

fMAX

[MHz]

Throughput kFFT/s

Logic

(LEs)

DSP

Blocks

M20Ks GFLOPS
Streaming FFT

4,096

477

116

3,412

48

43

28.5

4-way Parallel FFT (1.7 Giga-sample per second)

32,768

426

52

11,576

240

296

136

32-way Parallel FFT (10 Giga-sample per second in mid size Arria 10 device)

32,768

334

326

84,298

1,364

380

854

32-way Parallel FFT (64K points in mid size Arria 10 device)   

65,536

300

146

166,732

1,552

711

768