The combination of increased integration and a low-power Cyclone IV GX FPGA results in significant system-level benefits for a variety of applications:
- Portable or handheld battery-powered devices
- Space-constrained and other thermally challenging environments
- Price-sensitive applications where cooling systems are not cost effective
For more information about how you can lower your total cost of ownership and achieve higher reliability in your designs, due to fewer components, refer to the Decrease Total System Costs With Industry's Lowest Cost, Lowest Power FPGAs white paper (PDF).
Silicon and Architectural Optimizations
Static power can increase dramatically with the sub-micron semiconductor process if no power-reduction strategies are employed. Static power consumption rises at sub-micron process technologies largely because of increases in leakage current (including tunneling current across the thinner gate oxides), as well as sub-threshold leakage (channel and drain-to-source current).
Altera has taken significant steps to reduce static power in Cyclone IV FPGAs. By employing a low-power (LP) process technology traditionally used by major semiconductor manufacturers for handset components, Altera has minimized the leakage current for low static power. The smaller geometries made possible by this advanced process, combined with architectural optimizations, enable Cyclone IV FPGAs to keep dynamic and static power consumption to a minimum. The process and architectural enhancements that Altera employs with Cyclone IV FPGAs includes the use of low-k dielectrics, variable channel lengths and oxide thicknesses, and multiple transistor threshold voltages.
Accurate Power Estimation and Analysis
Altera supports power estimation and analysis, from design concept through implementation, with the most accurate and complete power management design tools. Altera is also the only programmable logic vendor that offers up to 125°C and worst-case silicon power estimates for the low-cost FPGA families throughout its tool suite. Altera offers the following power estimation and analysis resources:
Use the PowerPlay early power estimator (EPE) during the design concept phase and the PowerPlay power analyzer during design implementation. The PowerPlay EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization.
The PowerPlay power analyzer is a far more detailed power analysis tool that uses actual design placement and routing and logic configuration. The tool can use simulated waveforms to very accurately estimate dynamic power. The power analyzer, in aggregate, usually provides ± 10 percent accuracy when used with accurate design information. The Quartus Prime PowerPlay power models closely correlate to actual silicon measurements.
Altera uses more than 5,000 different test configurations to measure the power of individual components within a Cyclone series FPGA. Each configuration is focused on measuring a single circuit component of the FPGA in a specific configuration.
Quartus Prime Power Optimization
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area trade-offs have been automated within the register transfer level (RTL) through the place-and-route design flow.
Altera is a leader in bringing power optimization into the design flow. Quartus Prime PowerPlay optimization tools automatically use the Cyclone IV FPGA architecture capabilities to reduce power further, resulting in up to 25 percent lower dynamic power consumption compared to Cyclone III FPGAs. Combined with the silicon and architecture enhancements in the Cyclone IV FPGA family, these efforts have resulted in up to a 50 percent reduction in power consumption compared to 90-nm Cyclone II FPGAs.
The Quartus Prime development software has many automatic power optimizations that are transparent to the designer but provide optimal utilization of the FPGA architecture to minimize power. For example, with Quartus Prime software, you can:
- Transform major functional blocks.
- Map user RAMs so they use less power.
- Restructure logic to reduce dynamic power.
- Correctly select logic inputs to minimize capacitance on high-toggling nets.
- Reduce area and wiring demand for core logic to minimize dynamic power in routing.
- Modify placement to reduce clocking power.