Cyclone® devices began during a new era, one in which FPGAs have a more significant role in low-price, high-volume applications, in both new and existing FPGA markets. No longer restricted to peripheral uses, FPGAs now perform many critical processes within the system. When devices are used in important roles within systems they must be able to transfer data at high speeds with external memory devices when storage requirements exceed the abundant on-chip memory resources.
Cyclone devices are designed to communicate with double data rate (DDR) SDRAM and FCRAM and single data rate (SDR) SDRAM devices through a dedicated interface that ensures fast, reliable data transfer at up to 266 megabits per second (Mbps). Together with Cyclone-optimized, off-the-shelf intellectual property (IP) controller cores, designers can incorporate SDRAM and FCRAM devices into their systems in minutes.
DDR SDRAM & FCRAM Devices
DDR SDRAM devices have recently become popular primarily because of their low power consumption, relatively low cost, and ability to transfer data quickly. Data transactions occur on both edges of the clock, effectively doubling total data bandwidth over slower, SDR architectures. DDR SDRAM devices have penetrated markets beyond the personal computer (PC) space and are now widely used in a broad spectrum of applications, ranging from networking and communications to set-top boxes and home entertainment systems.
FCRAM devices are SRAM-like, low-latency devices based on the same fundamental architecture as SDRAM devices. They offer accelerated performance in applications that require large densities with SRAM-like performance yet consume less power. Similar to SDRAM devices, FCRAM devices support data transactions on both the rising and falling edges of the system clock. Their faster performance is directly attributed to proprietary pipeline and pre-charge operations that reduce the access cycle time significantly compared to SDRAM architectures.
Interface Technical Details
Each Cyclone device is equipped to interface with DDR SDRAM and FCRAM devices using optimized I/O pins as seen in Figure 1. Each I/O bank features two sets of interface signal pins and each set contains a single data strobe (DQS) pin and eight associated data (DQ) pins. These pins are designed for high-speed data transfer with an external memory device using the SSTL-2 Class II I/O standard. Up to 48 DQ pins are available per device with 8 corresponding DQS pins, supporting a single dual-inline memory module (DIMM) with 32-bit data and error correction.
Read operations from a memory device for a single data bit are depicted in Figure 2. The DQS signal is center-aligned with the incoming DQ signal and fed to the device's global clock network. The DQ signal is captured on both edges of the clock using FPGA registers and synchronized with the system clock using a second set of positive-edge-triggered core registers.
Write operations to memory devices for a single data bit are depicted in Figure 3. The DQS signal is sent to the memory device 90 degrees out-of-phase with the transmitted data. Output-enable logic is used to meet associated pre-amble and post-amble timing requirements.
The DQ signal is sent to the memory device on both edges of the in-phase system clock, using a set of logic registers and an output multiplexer that toggles between the data A and data B signals.