Stratix II FPGAs are available in the following variants:

  • Stratix II devices are based on a 1.2-V, 90-nm, SRAM process with 15,600 to 179,400 equivalent logic elements (LEs), up to 9 Mbits of on-chip RAM, up to 1,170 user I/O pins, and up to 384 (18x18) embedded multipliers in highly optimized digital signal processing (DSP) blocks
  • Stratix II GX devices fuse the Stratix II architecture with up to 20 full-duplex, high-performance, multi-gigabit transceivers. The transceivers deliver excellent jitter performance across the entire 600-Mbps to 6.375-Gbps operating range.

Stratix II Architecture

Stratix II Features

Feature Description
Architecture Performance and Efficiency
Industry's Biggest FPGA Built on 90-nm technology, Stratix II FPGAs provide unparalleled density and logic efficiency. Stratix II devices offer 5 percent more logic, 50 percent more memory, 4 times more digital signal processing (DSP) resources and 21 percent more user I/Os than competing FPGAs. Stratix II devices are well suited for ASIC prototyping applications where verification of a design prior to ASIC tape-out is vital.
Innovative Logic Structure Stratix II FPGAs are the product of an innovative logic architecture that achieves on average 50 percent faster performance with 25 percent reduced logic utilization compared to previous product families.
Differences Between Stratix II and Stratix Devices The Stratix II architecture, the industry's fastest FPGA architecture, offers advanced features based upon the highly successful Stratix architecture, with additional capabilities such as new logic structure, source-synchronous signaling with dynamic phase alignment (DPA) circuitry, and design security with configuration bitstream encryption technology.
Source-Synchronous Signaling, High I/O Bandwidth, and High-Speed Interfaces
Source-Synchronous Signaling I/O Standards in Stratix II Devices Stratix II devices offer 152 receiver and 156 transmitter channels that support source-synchronous signaling for data transfer rates as high as 1 Gbps.
Stratix II DPA Stratix II devices feature embedded DPA circuitry that simplifies PCB layout by eliminating signal alignment issues arising from skew-inducing effects when transmitting signals using source-synchronous signaling techniques over long distances.
Differential I/O Support Stratix II FPGAs offer high-speed differential I/O support for data rates up to 1 Gbps and address the high-performance needs of emerging I/O interfaces, including support for the LVDS, LVPECL, and HyperTransport™ standards.
Single-Ended I/O Standards in Stratix II Devices Stratix II devices support high-bandwidth, single-ended I/O interface standards (SSTL, HSTL, PCITM, and PCI-XTM) needed for today’s demanding system requirements.
Source-Synchronous Protocols Stratix II devices support a wide array of high-speed interface standards (SPI-4.2, SFI-4, 10 Gigabit Ethernet XSBI, HyperTransport, RapidIO®, NPSI, and UTOPIA IV) for flexibility and fast time-to-market.
Design Security
Design Security in Stratix II Devices Stratix II devices support design security with configuration bitstream encryption using the 128-bit Advanced Encryption Standard (AES) algorithm.
High Memory Bandwidth and High-Speed External Memory Device Interfaces
TriMatrix Memory in Stratix II Devices TriMatrix memory in Stratix II FPGAs offers up to 9 Mbits of RAM. This advanced memory structure includes three sizes of embedded RAM blocks—M512, M4K, and M-RAM blocks—that can be configured to support a wide range of features.
External Memory Interfaces in Stratix II Devices Stratix II devices provide advanced external memory interfaces, allowing designers to integrate external high-density SRAM and DRAM devices into complex system designs without degrading data-access performance.
High-Performance DSP
Stratix II DSP Blocks Stratix II devices include high-performance embedded DSP blocks, capable of running at 450 MHz, optimized for DSP applications. The DSP blocks eliminate performance bottlenecks in computationally intensive applications, provide predictable and reliable performance, and result in resource savings without compromising performance.
DSP Performance in Stratix II Devices Stratix II devices offer higher data processing capacity than DSP processors for maximum system performance.
Soft Multipliers in Stratix II Devices Stratix II devices provide a flexible implementation of soft multipliers that can be configured for different data width and latency. The soft multipliers provide very high DSP throughput in addition to the DSP blocks.
System Clock Management
Stratix II Clock Management Circuitry Each Stratix II device has up to 16 high-performance, low-skew global clocks that can be used for clocking high-performance functions or global control signals. Additionally, eight localized (regional) clocks per region increase the total number of clocks for any region to 24. This web of high-speed clock networks, which are tightly coupled with the abundant PLLs, ensures that the most complex design can run at optimal performance and with minimum clocking skew.
Stratix II Clock Management Features Stratix II devices feature up to 12 programmable PLLs, providing robust clock management and frequency synthesis capabilities for maximum system performance. The PLLs provide high-end features, including clock switchover, PLL reconfiguration, spread-spectrum clocking, frequency synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth. These features allow designers to manage system timing on and off the Stratix II device.
On-Chip Termination
On-Chip Termination in Stratix II Devices Stratix II devices feature series and differential on-chip termination that can simplify board layout by minimizing the number of external resistors needed on the PCB.
Remote System Upgrade Capabilities
Remote System Upgrades With Stratix II FPGAs Stratix II devices feature remote system upgrade capability, allowing error-free deployment of system upgrades from a remote location securely and reliably.
Automatic Cyclic Redundancy Code (CRC) Checking
CRC Stratix II devices feature automatic 32 bit CRC checking. A single click in Quartus® II software simplifies setup and activates the device's built-in CRC checker. It is the most cost effective FPGA solution available for single event upset (SEU).
Embedded Soft Embedded Core Processor
Stratix II Devices and Nios® II Processors The advanced architectural features of Stratix II devices combined with the Nios II family of embedded processors offer unparalleled processing power to meet the needs of network, telecommunications, DSP applications, mass storage, and other high-bandwidth systems. Stratix II devices improve overall system performance of the latest Nios II processors.

Stratix II GX FPGA Transceiver Features Summary

Feature Description
Excellent Signal Integrity The transmitter has low jitter generation and up to 500 percent pre-emphasis. The receiver has excellent jitter tolerance, and up to 17-dB equalization, which can either be continuously and automatically adjusted by an on-chip controller, or set statically.
Low Power The transceiver dissipates 225 mW per channel at 6.375 Gbps, and only 125 mW per channel at 3.125 Gbps.
PCS Support (Hard IP) The transceiver supports the following PCS blocks: PCI Express, PIPE-Compliant PCS, CEI-6G-LR/SR, 8b/10b encoder/decoder, XAUI state machine and channel bonding, Gigabit Ethernet state machine, SONET, and 8b/10b and 8/10/16/20/32/40-bit interface (to FPGA logic).
System-Level Diagnostics Serial loopback, reverse serial loopback, pseudo-random binary sequence (PRBS) generator and checker, and the registered-based interface facilitate dynamic reconfiguration of pre-emphasis, equalization, and differential output voltage.
Feature Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Adaptive Logic Modules (ALMs) (1) 6,240 13,552 24,176 36,384 53,016 71,760
Equivalent LEs (1) 15,600 33,880 60,440 90,960 132,540 179,400
M512 RAM Blocks (512 Bits + Parity) 104 202 329 488 699 930
M4K RAM Blocks (4 Kbits + Parity) 78 144 255 408 609 768
M-RAM Blocks (512 Kbits + Parity) 0 1 2 4 6 9
Total RAM bits 419,328 1,369,728 2,544,192 4,520,448 6,747,840 9,383,040
DSP Blocks 12 16 36 48 63 96
Embedded 18-Bit x 18-Bit Multipliers (2) 48 64 144 192 252 384
Phase-Locked Loops (PLLs) (3) 6 6 12 12 12 12
Maximum User I/O Pins 366 500 718 902 1,126 1,170
Availability Buy Now Buy Now Buy Now Buy Now Buy Now Buy Now
  1. Each ALM is equivalent to 2.5 LEs.
  2. Each DSP block in a Stratix II device can implement four 18×18 multipliers or one 36×36 multiplier. To obtain the total number of 36×36 multipliers per device, divide the total number of 18×18 multipliers by a factor of 4.
  3. Includes both fast and enhanced PLLs.
Package Size
(mm x mm)
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
484-Pin FineLine BGA (FBGA) Package
(23 x 23)
342 342 334      
484-Pin Hybrid FBGA
(27 x 27)
      308 (1)    
672-Pin FBGA
(27 x 27)
366 500 492      
780-Pin FBGA
(29 x 29)
      534 (1) 534 (1)  
1,020-Pin FBGA
(33 x 33)
    718 758 742 742
1,508-Pin FBGA
(40 x 40)
      902 1,126 1,170

User I/O counts are preliminary and subject to change.

Device Package (1) Speed Grade
EP2S15 484-pin FBGA
672-pin FBGA
EP2S30 484-pin FBGA
672-pin FBGA
EP2S60 484-pin FBGA
672-pin FBGA
1,020-pin FBGA
EP2S90 780-pin FBGA
1,020-pin FBGA
1,508-pin FBGA

780-pin FBGA
1,020-pin FBGA
1,508-pin FBGA


1,020-pin FBGA
1,508-pin FBGA


BGA: ball-grid array
FBGA: FineLine BGA package
MBGA: Micro FineLine BGA package
UBGA: Ultra FineLine BGA package
PDIP: plastic dual in-line
PLCC: plastic J-lead chip carrier
PQFP: plastic quad flat pack
RQFP: power quad flat pack
SOIC: small-outline integrated circuit
TQFP: thin-quad flat pack

Feature Device
Transceiver Data Rate 600 Mbps–6.375 Gbps
Adaptive Logic Modules (ALMs) (2) 13,552 24,176 36,384 53,016
Equivalent LEs (2) 33,880 60,440 90,960 132,540
LVDS Channels 29 29 45 78
M512 RAM Blocks 202 329 488 699
M4K RAM Blocks 144 255 408 609
M-RAM Blocks 1 2 4 6
Total RAM Bits 1,369,728 2,544,192 4,520,448 6,747,840
DSP Blocks 16 36 48 63
Embedded 18-Bit x 18-Bit Multipliers (3) 64 144 192 252
PLLs (4) 4 4/4/8 8 8
Availability Buy Now Buy Now Buy Now Buy Now
  1. Features are preliminary and subject to change.
  2. Each ALM is equivalent to 2.5 LEs.
  3. Each DSP block in Stratix II GX devices can implement four 18×18 multipliers or one 36×36 multiplier. To obtain the total number of 36×36 multipliers per device, divide the total number of 18×18 multipliers by a factor of 4.
  4. Includes both enhanced PLLs and fast PLLs.
Device Transceiver Channels LVDS Channels Device Package and User I/O
Receive Transmit F780 (29 mm) User I/O Pins F1152 (35 mm) User I/O Pins F1508 (40 mm) User I/O Pins
EP2SGX30C 4 31 29 361
EP2SGX60C 4 31 29 364
EP2SGX30D 8 31 29 361
EP2SGX60D 8 31 29 364
EP2SGX60E 12 42 (3) 42 534
EP2SGX90E 12 47 (3) 45 558
EP2SGX90F 16 59 (3) 59 650
EP2SGX130G 20 73 (3) 71 734
  1. The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock-reference pins for high-speed I/O capability.
  2. User I/O counts are preliminary and subject to change.
  3. Includes two differential clock inputs that can also be used for two additional channels for the differential receiver.
Device Package Speed Grade
EP2SGX30D 780-pin FBGA -4
EP2SGX60D 780-pin FBGA -4
EP2SGX60E 1,152-pin FBGA -4
EP2SGX90E 1,152-pin FBGA -4
EP2SGX90F 1,508-pin FBGA -4
EP2SGX130G 1,508-pin FBGA -4