Stratix II GX Density & Logic Efficiency

With up to 130K equivalent logic elements (LEs) and more than 6.7 Mbits of embedded RAM, Altera’s Stratix® II GX device family offers the industry’s fastest FPGAs with sufficient logic resources. At more than triple the logic elements of Stratix GX devices, Stratix II GX devices have a new and innovative logic structure that offers higher performance and better logic efficiency. Built on a state-of-the-art 90-nm manufacturing process, the new logic structure of Stratix II GX FPGAs increases performance by 50 percent and uses 25 percent less logic resources compared to Stratix and Stratix GX devices. Table 1 shows the density and resources available in Stratix II GX FPGAs.

Table 1. Stratix II Density & Resources

Device Adaptive Logic Module (ALM) Adaptive Look-Up Table (LUT) Equivalent LEs Total Memory Bits 18x18 Multiplier Phase-Locked Loops (PLLs)
EP2SGX30C/D13,55227,10433,8801,369,728644
EP2SGX60C/D/E24,17648,35260,4402,544,1921448
EP2SGX90E/F36,38472,76890,9604,520,4481928
EP2SGX130G53,016106,032132,5406,747,8402528

Innovative Logic Element Structure

Stratix II GX devices are built with highly flexible adaptive logic modules (ALMs) that are optimized to maximize logic efficiency and performance (shown in Figure 1). The inputs of a single ALM can be flexibly divided between the two output functions, allowing wide input functions to run fast and narrow input functions to efficiently use remaining resources.

Figure 1. Stratix II GX ALM

A Stratix II GX ALM can be programmed into one of the configurations in Table 2. More Stratix II GX configuration information can be found in the Stratix II GX Handbook and Stratix II Handbook.

Table 2. Stratix II GX Density & Resources

Configuration Description
Adaptive LUTCombinational mode of two functions with up to six inputs each, depending on input sharing. Includes two 4-input backwards compatibility mode to first-generation Stratix devices.
Extended LUTCombinational mode of selective 7-input functions.
ArithmeticArithmetic functions of two 4-input LUTs.
Shared ArithmeticArithmetic function of three numbers in one carry chain.

The ability to expand and share the LUT inputs allows each Stratix II GX ALM to absorb more logic capacity than traditional 4-input LUT structures for an equivalent function. The larger logic capacity in Stratix II GX ALMs not only reduces the total logic utilization but also reduces the average routing utilization (shown in Figure 2).

High density FPGAs experience increased average routing utilization, which increases the total register-to-register delays. Routing delays start to dominate total register-to-register delays as design size gets larger and larger. Designs above 100K LEs can have routing delays of up to 80 percent of total delay. Stratix II GX devices address this issue by lowering the largest component of core delays and thereby increasing clock frequency.

Figure 2. Stratix II GX Devices Reduce Average Routing Utilization

ALM Performance Advantages

The Stratix II GX ALM goes beyond the traditional 4-input-LUT structure and extends the logic capacity to efficiently construct any logic functions with 5, 6, or 7 inputs. With ALM’s ability to implement functions with higher input counts, the Stratix II GX logic structure offers an average performance improvement of 50 percent and 25 percent efficiency improvement by:

  • Reducing the number of logic levels required for the overall combinatorial logic
  • Reducing the extra programmable routing needed in the 4-input-LUT implementation
  • Reducing the stress on the demand for general routing resources