Stratix GX Transceiver Protocols

Versatile Stratix® GX transceiver blocks support the many emerging protocols in the market that require high-speed differential I/O with clock data recovery (CDR). Some examples include SerialLite, 10 Gigabit Ethernet support via the 10-Gbps attachment unit interface (XAUI), a SONET/SDH scrambled backplane, and custom implementations. Support for a wide spectrum of protocols means Stratix GX devices can be used in many different applications, as shown in Figure 1.

Figure 1. CDR Protocols: Applications & Interconnect Types

Table 1 provides more information on the various protocols suitable for implementation in Stratix GX devices.

Table 1: Standard Protocols Implemented in Stratix GX FPGAs

Feature SerialLite 10 Gigabit
Ethernet XAUI
Maximum Bandwidth (Gbps)5112.512.51.2510801.4852.488
Bus Width1-25641, 4111, 2, 4, 8, 12, 1611
Maximum Single Channel Rate (Gbps)3.18753.1253.1251.253.18752.51.4852.488


The SerialLite protocol was designed as a lightweight, point-to-point protocol aimed at providing a small footprint, low latency, and low overhead. Using SerialLite in Stratix GX devices provides designers with a low-risk path for implementing serial I/O standards in their applications.

10 Gigabit Ethernet XAUI

XAUI is designed as an interface extender for the 10-gigabit media-independent interface (XGMII). XAUI can be used in various applications including 10-gigabit Ethernet line cards, LAN-to-WAN bridges (Ethernet to SONET/SDH converter), and as a backplane and chip-to-chip interconnect. The XAUI specification uses four full-duplex serial links operating at 3.125 Gbps in each direction. In aggregate, a total of 12.5 Gbps can be transferred in each direction. The 8B/10B encoding/decoding overhead supports a 10 Gbps throughput. The protocol can also accommodate SONET/SDH OC-192 traffic at those rates.

As shown in Figure 2a, Stratix GX devices have been designed for easy implementation of XAUI. Higher-level layers can be implemented in the programmable logic section of the device, including reconciliation, MAC, switching functions, and a protocol bridge. In addition, the gigabit transceiver block contains the required components for implementing the physical layer of XAUI, as shown in Figure 2b. The physical layer of XAUI, also known as the XGXS, contains the XAUI sublayers PCS, PMA, and PMD. For more details regarding the transceiver block visit the Stratix GX Transceiver page.

Figure 2a: Implementing XAUI in Stratix GX Devices

Figure 2b: Implementing XAUI in Stratix GX Devices

The 10-Gigabit Ethernet Technology Center page contains more resources, including intellectual property (IP) cores on 10 Gigabit Ethernet XAUI.

Serial RapidIO

RapidIO™ technology is a high-performance, packet-switched interconnect technology designed to pass data and control information between microprocessors, digital signal processors, communications and network processors, system memories, and peripheral devices. Stratix GX devices are compatible with this standard. The new serial link specification from the RapidIO trade association uses the parallel RapidIO protocol from the link layer upwards, but with serial rates of 1.25, 2.5 and 3.125 Gbps in the physical layer. The Serial RapidIO protocol can be used in backplanes and chip-to-chip applications. For more resources, including IP cores on RapidIO visit the RapidIO Technology Center page.

Gigabit Ethernet

Stratix GX devices can be used to implement the Gigabit Ethernet PHY and MAC in a single device. The Gigabit Ethernet Technology Center page contains more resources, including IP cores on Gigabit Ethernet.

Fibre Channel

Fibre Channel is a data transfer interface technology that maps several common transport protocols, including Internet protocol and SCSI, allowing it to merge high-speed I/O and networking functionality in a single connectivity technology. Fibre Channel operates at up to 2.125 Gbps. The combination of the Stratix GX gigabit transceiver block and high-performance logic array creates a powerful Fibre Channel solution. The Fibre Channel Technology Center page contains more resources, including IP cores on Fibre Channel.

PCI Express

PCI Express (formerly 3GIO) uses differential CDR signaling to allow transmission of high-speed data while maintaining compatibility with the current PCI software environment. It can be used for chip-to-chip and add-in card applications to provide connectivity for adapter cards, as a graphics I/O attach point for increased graphics bandwidth, and an attach point to other interconnects like 1394b, USB 2.0, InfiniBand architecture and Ethernet. Some of the advanced features of the protocol include aggressive power management, quality of service (QoS), isochrony, hot attach/detach, and reliability, availability, serviceability (RAS) features. The PCI Express Technology Center page contains more resources, including IP cores on PCI Express.


The Society of Motion Picture and Television Engineers (SMPTE) specification 292M is used in HDTV studios that must support a network of various equipment sets at high-definition rates. Video and embedded audio is transported between equipment over coaxial cable using the serial digital video interface (SDI) transmission standard. The high-definition standard for SDI requires up to 1.485-Gbps serial data rates, as defined by SMPTE specification 292M.

SONET/SDH or Custom Backplane

Custom backplane interfaces can be implemented in Stratix GX devices by enabling and disabling various blocks within the transceiver. 8B/10B encoding/decoding can be included or turned off. For example, a SONET/SDH backplane would not use 8B/10B encoding, it would instead use a scrambler in the logic array. Furthermore, the embedded pattern detector can be used for scrambled data and other types of encoding/decoding schemes.